
Renewable energy technologies such as solar, thermal, wind, hydro, bio-fuels, fuel cells etc. are becoming trendy and being commissioned in large-scales, due to their environmental friendliness and energy sustainability. This manuscript focuses on alternative energy based-on thermoelectricity, particularly thermoelectric generators (TEGs). From the literature review, there is less emphasis on how multiple TEGs can be best configured electrically for optimum operations. In light of this, Matlab/Simulink were employed to institute a unique theoretical framework, that can easily be comprehensively used to simulate thermoelectricity parameters, with focus to determine TEG modules (of any quantity/configuration) optimal resistance matching and performance. The principal findings of the study are; 1) the effects of TEGs internal resistance, which proportionally causes output voltage drop and power loss as well as efficiency loss and 2) TEG modules may not be connected anyhow in series and or in parallel, but in a setup that gives a total electrical resistance that matches the load electrical resistance. Thus, TEGs should be a) of the same model with the same or approximate internal resistance, b) in a configuration whereby the TEGs total resistance equals the load resistance, as doing so ensures maximum power is transferred between the source (TEGs) and the electrical load and c) preferably be in a symmetrical electrical configuration. A symmetrical electrical configuration ensures ⅰ) the TEG modules total output resistance, irrespective of the quantity used, approximates that of a single TEG, with the overall TEG modules simply becoming now one large powerful TEG having an equivalent resistance of a single TEG and ⅱ) the TEGs power, voltage and current operations are optimal.
Citation: Nganyang Paul Bayendang, Mohamed Tariq Kahn, Vipin Balyan. Thermoelectric Generators (TEGs) modules—Optimum electrical configurations and performance determination[J]. AIMS Energy, 2022, 10(1): 102-130. doi: 10.3934/energy.2022007
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Renewable energy technologies such as solar, thermal, wind, hydro, bio-fuels, fuel cells etc. are becoming trendy and being commissioned in large-scales, due to their environmental friendliness and energy sustainability. This manuscript focuses on alternative energy based-on thermoelectricity, particularly thermoelectric generators (TEGs). From the literature review, there is less emphasis on how multiple TEGs can be best configured electrically for optimum operations. In light of this, Matlab/Simulink were employed to institute a unique theoretical framework, that can easily be comprehensively used to simulate thermoelectricity parameters, with focus to determine TEG modules (of any quantity/configuration) optimal resistance matching and performance. The principal findings of the study are; 1) the effects of TEGs internal resistance, which proportionally causes output voltage drop and power loss as well as efficiency loss and 2) TEG modules may not be connected anyhow in series and or in parallel, but in a setup that gives a total electrical resistance that matches the load electrical resistance. Thus, TEGs should be a) of the same model with the same or approximate internal resistance, b) in a configuration whereby the TEGs total resistance equals the load resistance, as doing so ensures maximum power is transferred between the source (TEGs) and the electrical load and c) preferably be in a symmetrical electrical configuration. A symmetrical electrical configuration ensures ⅰ) the TEG modules total output resistance, irrespective of the quantity used, approximates that of a single TEG, with the overall TEG modules simply becoming now one large powerful TEG having an equivalent resistance of a single TEG and ⅱ) the TEGs power, voltage and current operations are optimal.
Abbreviations: A: TEG p-n junction thermocouple area in m2; C: Configuration; C1−10: Configurations 1 to 10; ∆T: TEG(s) temperature difference (Th–Tc) in ℃ or kelvin; I: TEGs output current in ampere through the TEG(s); IMax: TEG(s) maximum output current in ampere; ITEG_Ci: TEG converter input current in ampere; ITEG_Co: TEG converter output current in ampere; ITEG_Int = ITEGRtint: TEG internal resistance current in ampere; ITEG_OC = TEGIoc: TEG ideal current in ampere; K: TEG(s) thermal conductance in (W/K); L: TEG p-n junction thermocouple length in meter; MPP: maximum power point; MPPT: maximum power point tracking; N: TEG modules quantity used in the configuration; n: TEG manufacturer p-n thermocouples amount used in a TEG; ɳ: TEG(s) thermal/electrical/conversion efficiency; ρ: TEG electrical resistivity in Ωm; Po: TEG(s) output power in watt, is the difference between Qh and Qc; PTEG_Ci: TEG converter input power in watt; PTEG_Co: TEG converter output power in watt; PTEG_Int = PTEGRtint: TEG internal resistance power in watt; PTEG_OC = TECPocM: TEG ideal power in watt; Qc: TEG heat emitted on TEG module(s) cold-side in watt; Qh: TEG heat absorbed on TEG module(s) hot-side in watt; r: Thermoelectric device P-N thermocouples unit resistance in ohm; R: TE device (TEG) module unit resistance in ohm; RL: TEGs electrical load resistance in Ω connected to the TEG(s) output; Rt: TEG module(s) total resistance in ohm; RTEG_Int = TEGRtint: TEG internal resistance in ohm; S: TE device Seebeck coefficient in V/K; TE: Thermoelectric; TECs: Thermoelectric coolers (TEC modules); TEGs: Thermoelectric generators (TEG modules); TEG-S = Ts: TEG modules in series; TEG-P = Tp: TEG modules in parallel; Tc: Temperature on TEG cold-side in ℃; Th: Temperature on TEG hot-side in ℃; Tp: TEGs quantity in parallel; Ts: TEGs quantity in series; Tt: TEG total quantity; Vo: TEG module(s) output voltage in volt; VTEG_Ci: TEG converter input voltage in volt; VTEG_Co: TEG converter output voltage in volt; VTEG_Int = VTEGRtint: TEG internal resistance voltage in volt; VTEG_OC = TEGVoc: TEG ideal voltage in volt; Z: TE device figure of merit in per kelvin; Z−T: TE device average dimensionless figure of merit based on mean temperature
It's no secret that sustainable, renewable and alternative energy sources demands are on the rise to augment the grid and for personal use. In this regard, thermoelectricity is investigated as a potential alternative for basic household clean energy use—such as DC power, lighting and cooling/heating. Thermoelectricity as examined in [1], constitutes the Seebeck, Peltier and Thomson effects. The latter has trivial practical use, therefore the practical focus is on the Seebeck and Peltier effects. Seebeck effect entails production of DC power from heat using a TEG, whereas Peltier effect entails cold/heat generation from DC electricity depending on the applied voltage polarity across a TEC. This paper focuses on TEGs. In an effort to improve the TEG power output, noted in [2] is how a TEG module DC power can be enhanced by properly matching the TEG internal resistance to the electrical load, increasing the TEG hot-side temperature and lowering the TEG cold side temperature, increasing the heat flux density, increasing the number of TEG units, using DC to DC converters and energy management control techniques. Further, researched in [3], is the thermo-power properties of a single module relative to the electrical load resistance, whereas proposed in [4], is a bi-directional model that enables a thermoelectric device to be operated as a TEG and as a TEC with both cooling and heating. A charge pump system for a flexible TEG was studied in [5], whereby high output impedance from a TEG can be tuned to match the load impedance; meanwhile investigated in [6], is the design of a linear-shaped TEG in which the p-n junction thermoelements length can be flexibly optimised independently. Proposed in [7] is a general method to optimize the structure and load current for a segmented TEG module, where the hot and cold junction materials are respectively skutterudite and bismuth telluride. ANSYS was employed in [8] to find the optimal design of one pair of a p-n junction leg of a very basic TEG model using three-dimension, whereas provided in [9], are fundamental insights on the operation of TEGs in physical environments by depicting the combinational effect of thermoelectric materials properties, device boundary conditions and environmental thermal resistivity on TEG performance in conjunction with the module parameters. The opposing requirements for the performance and reliability of a TEG using numerical finite element analysis simulations were examined in [10], by considering the parameters that significantly influence the operational performance and structural reliability of a TEG. Furthermore, the mechanisms as well as strategies for enhancing thermoelectric efficiency by looking at advances in thermoelectric materials was reviewed in [11], whereas assessed in [12], are the principles and advances to develop TEG materials from organic and or inorganic materials. A systematic review of the potential application of TEGs for use as power sources in wearable electrocardiographic monitoring systems was provided in [13], whereas employed in [4], is a novel thermal diffusion method to fabricate n-type Te-embedded Bi2Te3 flexible thin films on flexible polyimide substrates. Investigated in [15] are state of the art of TEGs—in which latest thermoelectric modules are introduced as well as TEG applications in transport, homes, industries, space, miniature generation and solar heat-to-power conversion. TEG for use in internet of things was studied in [16], in which the market growth and needs are identified, various energy harvesters and their merits presented, heat sources quantified, TEGs topologies and materials performance reviewed as well as TEGs energy management strategies compared. The review and analysis of fabrication of TEG nano-composite materials and devices for internet of things applications were examined in [17], whereas in [18], the state-of-the-art of TEGs is reviewed comprehensively, by examining the materials used in TEGs, figure of merit, improvement techniques introduced, different configurations of experimental set-ups and prototypes explored and as well the investigation of TEGs performance using different simulation software packages. In all of these studies, emphasis on the different TEG modules electrical configurations for optimal results when connecting many TEGs together for more output power, has been seldom studied/reported. With these research gap identified, we zoom-in on TEGs source to load resistance matching, to study the optimal electrical configurations when connecting many TEG modules together to efficiently generate more power. Our manuscript is arranged as follows: proceeding the introduction is a brief TEGs applicable maths, followed by TEGs modelling and simulation using Matlab/Simulink—whereby 100 TEGs are simulated in ten different series and or parallel configurations to determine the optimum configurations with respect to the electrical load and finally the different simulated results are presented, comparatively engaged and the closing remarks drawn.
From [1,2,12,18] extensive literature reviews, multiple TEG modules are connected in series and or parallel to increase the output power. However, there is inadequate in-depth research on the significance of the TEG modules different electrical configurations. It should be noted that a TEG is a voltage source and to transfer maximum power between a source and a load, the source and load resistances or impedances must matched. A TEG is not an ideal voltage source; as a result, it's imperative its internal resistance is scrutinized when connecting multiple TEGs to increase their DC output power, since the internal resistance will either increase, decrease or stays approximately the same depending on the quantity of TEGs and the configuration used, which will consequently affects the TEG output power and most importantly the efficiency—hence the main research focus of this paper. TEG steady-state maths is extensively presented in [19] and herein, it is briefly developed further for TEGs, to study the total resistance and power output as well as efficiency, when multiple TEG modules are differently connected in series and or in parallel.
It's worth noting that connecting many TEGs in series to boost the output voltage, also boosts the TEGs total internal resistance and connecting many TEGs in parallel to increase the output current, also decreases the TEGs total internal resistance. For easy insight, TEGs static (constant property model) maths is then developed as follows:
The thermoelectric (TE) device p-n thermocouples unit resistance (r) in ohm is:
r=LρA(Ω) | (1) |
where L is the TEG p-n junction thermocouple length in meter (m), ρ is the TEG electrical resistivity in Ωm and A is the TEG p-n junction thermocouple area in metre squared (m2).
The TE device (TEG) module unit resistance (R) in (ohm) is calculated as:
R=r n(Ω) | (2) |
where n which differs, is the TEG's manufacturer p-n thermocouples quantity used.
The TEG module(s) or TEG(s) total resistance (Rt) in (Ω) can be derived as:
Rt=rnTsTp=RTsTp(Ω) | (3) |
where Ts and Tp are the TEGs respective amount in series and parallel. NB: for Eq 3 to be valid, all the TEGs used must be of the same type to ensure R is very identical. Applied in Eq 3, is simply the standard resistance formula used to calculate total electrical resistance, assuming all the electrical resistances in a circuit are the same.
The TEG module(s) generated current (I) in ampere is calculated as:
I=nSΔTRL+Rt(A) | (4) |
where S is the TE device Seebeck coefficient in V/K, RL is the electrical load resistance in Ω connected to the TEG(s) output and ∆T is the TEG(s) temperature difference in ℃ or K.
The TEG module(s) generated voltage (Vo) in volt is derived as:
Vo=IRL=n[SΔT]−IRt(V) | (5) |
where ∆T = Th – Tc is the TEG(s) temperature difference in ℃ or kelvin in which Th and Tc are respectively the temperatures on the TEG hot and cold sides in ℃ or K and I is the output current in ampere through the TEG(s). I is normally responsible for the TEG(s) internal Ohmic or Joule heating—which negatively affects the internal working of the TEG(s) if not controlled within optimal operational limit.
Heat absorbed on TEG module(s) hot-side (Qh).
For the TEG(s) to generate power, the TEG(s) hot-side must be at a high temperature Th to absorb more heat and create a constant heat flux (Qh) in watt, given as:
Qh=n[(SITh)+(KΔT)]−0.5I2Rt(W) | (6) |
where K is the TEG(s) thermal conductance in (W/K)
Heat emitted on TEG module(s) cold-side (Qc)
For the TEG(s) to generate power, the TEG(s) cold-side must be at a lower temperature Tc to dissipate the heat Qc in watt, given as:
Qc=n[(SITc)+(KΔT)]+0.5I2Rt(W) | (7) |
TEG module(s) generated power (Po)
The TEG(s) output power in watt, is the difference between Qh and Qc or the product of the generated voltage and current, given variously as:
Po=Qh−Qc=n[(SIΔT)]−I2Rt(W) | (8) |
Po=IVo=n[(SIΔT)]−I2Rt(W) | (9) |
TEG(s) conversion efficiency (ɳ)
This is the ratio of the TEG(s) output power and the heat absorbed on the TEG(s) hot-side.
η=Po/Qh | (10) |
It should be noted that the above sets of equations are just the fundamental mathematical expressions necessary to define TEG(s) and for use to formulate the case for connecting more than one TEG in series/parallel to generate more power. The major electrical difference between a TEG and TEG(s) is the number of modules used and as a result, their different electrical capabilities. Figure 1 depicts the overview of the modeled TEG(s) electrical analysis. For this study, an interleave boost converter with maximum power point tracking is used; however, the details and operations are not discussed, because the settings were constant throughout for all the TEGs configurations analysis.
Summarized in Figure 2 is the simulated workflow of the study, in which the TEGs basic steady-state maths is expressed, followed by the modeling and finally simulation of the various configurations using Matlab and Simulink.
In Section 2.1, TEGs fundamental equations of interests were examined with keen emphasis on the total internal resistance Rt —which was derived and further used to develop and express in terms of Rt the standard TEG equations to now cover the case for TEG(s). These equations were henceforth modeled using Matlab and Simulink to establish a simple TEG(s) theoretical model that can be used to simulate and determine TEGs optimal electrical configurations with respect to a load. The detailed modeling is not covered in this article besides the user's interface and the results. Represented in Figure A1a (see supplementary link) is the main TEGs simulated model, in which an infinite amount of TEGs configurations and the TEGs parameters expressed in Section 2.1, can be configured and simulated to obtain TEG(s) optimum results—the idea is to match the TEGs source and load resistances. Usually, RL is first set and the simulation is executed to continuously check and match the TEGs total internal resistance for maximum power transfer at different simulation times which correspond to the different TEGs configurations. Let's assume a heat energy harvesting system is to be designed to use 'X' amount of TEGs modules, normally in the literature, it's a matter of dividing the total output power required by the amount of power a TEG can generate to get the 'X' amount of TEGs required. In-depth research on the optimal number and in what optimum electrical configurations with respect to the load is lacking. Lets further assume this computed 'X' amount of TEGs happens to be 102.3 or 97.6; in the literature, it's also a matter of just rounding down to 102 or up to 98 and further connecting the TEGs in series/parallel to get the needed output power—which might not be efficient/optimal. We hereby advance the case for using multiple TEGs, whereby emphasis on the TEGs optimal electrical configurations with respect to the load must first be determined. Table 1 portrays a typical TEG parameters/specifications found in [20] and lets assume instead of normally using 102 or 98 TEGs, 100 TEGs is proffered, from which the 100 TEG modules are further analyzed in 10 different electrical configurations to determine their different electrical resistance (as exemplified in Table 2), as well as their optimal electrical outputs.
S (µV/K) | r (mΩ) | n | R (Ω) | Z (K-1) | ZT | Th (℃) | Tc (℃) | Vout (V) | Iout (A) | Pout (W) |
375 | 12 | 127 | 1.524 | 0.00191 | 0.7125 | 200 | 50 | 3.558 | 2.353 | 8.371 |
C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | |
TEG_S | 100 | 50 | 25 | 20 | 10 | 10 | 5 | 4 | 2 | 1 |
TEG_P | 1 | 2 | 4 | 5 | 10 | 10 | 20 | 25 | 50 | 100 |
Rt = RL (Ω) | 152.4 | 38.1 | 9.525 | 6.096 | 1.524 | 1.524 | 0.381 | 0.24384 | 0.06096 | 0.01524 |
Our rationale is to take for example the 100 TEG modules, find the factors of 100 (1, 2, 4, 5, 10, 20, 25, 50,100) and arrange them in different series, parallel and series-parallel (mixed) combinations pairs to get 10 unique electrical configurations from the 100 TEGs, as shown in Table 2. By using Eq 3 to compute the total resistance Rt for each of this unique configurations (C) denoted C1–C10, each gives unique Rt. The following conditions must be met ⅰ) all the TEGs used must be the same model to have similar r or R, ⅱ) to test run each configuration (C1–C10), the load resistance RL, must first be changed to equal the TEGs configuration Rt to obtain the maximum power for that specific configuration and iii) all other parameters must be treated as a constant/ideal, to ensure the test conditions for each C1–C10 is the same—that is, the TEGs thermal resistance is ideal, all TEGs parameters are temperature invariant, all TEGs have even temperature distribution, the interleave boost converter and MPPT function settings are constant across. The TEGs in series are denoted TEG_S and in parallel TEG_P. NB: The same rationale applies to thermoelectric coolers (TECs); however, unlike TEG which is a voltage source that supplies power, TEC is an electrical load that requires power supplied to it. Presented in Section 3 are the simulation results. It should be noted this is a theoretical study with key focus on only studying different TEGs configuration source to load electrical resistance matching and maximum power transfer, which is based solely on the TEG modules different configurations (10 in this case) without considering any other factor in this study.
Tables 3–12 and Figures A1–A10 (see supplementary file link for raw details) depict the 100 TEGs in 10 unique electrical configurations, as well as their simulation results used to determine the optimal electrical configurations.
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/ Time |
VTEG_Ci/ Time |
ITEG_Ci/ Time |
PTEG_Co/Time | VTEG_Co /Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||
C1 | 100 | 1 | 152.4 | Peak | 941.8/0.65 | 243.4/0.246 | 226.6/1 | 704.6/1.031 | 327.7/1.031 | 2.15/1.031 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 74.814 | ||||||||
MPP | 908.5/0.175 | 203.5/0.175 | 4.465/0.175 | 386.2/0.246 | 242.6/0.246 | 1.592/0.246 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 42.509 | ||||||||||||
Actual | 458.3/0.1 | 116.9/0.1 | 3.92/0.1 | 88.45/0.1 | 116.1/0.1 | 0.7618/0.1 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 19.299 | ||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||
C1 | 100 | 1 | 152.4 | Peak | 2342/0.1 | 597.5/0.1 | 226.6/1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 226.6/0.1 | 33.127 | |||||||||||
MPP | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 4.28/0.114 | 31.956 | |||||||||||||||
Actual | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2801/0.1 | 714.4/0.1 | 3.92/0.1 | 16.362 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci /Time | VTEG_Ci /Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co /Time | ITEG_Co /Time | Ts /Time | Tp/Time | Tt /Time | Rt (Ω)/Time | |||||||
C2 | 50 | 2 | 38.1 | Peak|*MPP | 915.3/0.23 | 173.7/0.261 | 5.609/0.174 | *784.7/0.261 | 172.9/0.261 | 4.538/0.261 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 85.731 | |||||
Actual | 822.3/0.2 | 154.8/0.2 | 5.312/0.2 | 622.6/0.2 | 154/0.2 | 4.042/0.2 | 50/0.2 | 2/0.2 | 100/0.2 | 38.1/0.2 | 75.714 | |||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||
C2 | 50 | 2 | 38.1 | Peak | 2581/0.109 | 624.8/0.1 | 5.609/0.174 | 152.4/0.1 | 3043/0.123 | 714.4/0.1 | 5.609/0.174 | 30.079 | ||||||||
Actual | 1075/0.2 | 202.4/0.2 | 5.312/0.2 | 38.1/0.2 | 1897/0.2 | 357.2/0.2 | 5.312/0.2 | 43.347 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C3 | 25 | 4 | 9.525 | Peak|*MPP | 882.3/0.279 | 91.16/0.292 | 9.833/0.268 | *857.5/0.292 | 90.37/0.292 | 9.488/0.292 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.189 | |||||||||||
Actual | 836.9/0.3 | 90.84/0.3 | 9.213/0.3 | 828.4/0.3 | 88.83/0.3 | 9.326/0.3 | 25/0.3 | 4/0.3 | 100/0.3 | 9.525/0.3 | 98.996 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_Int /Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C3 | 25 | 4 | 9.525 | Peak | 3154/0.129 | 673.5/0.1 | 9.833/0.268 | 152.4/0.1 | 3427/0.138 | 714.4/0.1 | 9.833/0.268 | 25.745 | ||||||||||||||
Actual | 808.5/0.3 | 87.76/0.3 | 9.213/0.3 | 9.525/0.3 | 1645/0.3 | 178.6/0.3 | 9.213/0.3 | 50.875 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C4 | 20 | 5 | 6.096 | Peak|*MPP | 887.4/0.423 | 73.68/0.431 | 12.1/0.419 | *871.6/0.431 | 72.89/0.431 | 11.96/0.431 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 98.219 | |||||||||||
Actual | 837.1/0.4 | 71.94/0.4 | 11.64/0.4 | 830.3/0.4 | 71.14/0.4 | 11.67/0.4 | 20/0.4 | 5/0.4 | 100/0.4 | 6.096/0.4 | 99.187 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_Int /Time | RTEG_Int /Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C4 | 20 | 5 | 6.096 | Peak | 3321/0.134 | 686.5/0.1 | 12.1/0.419 | 152.4/0.1 | 3525/0.141 | 714.4/0.1 | 12.1/0.419 | 25.174 | ||||||||||||||
Actual | 825.4/0.4 | 70.93/0.4 | 11.64/0.4 | 6.096/0.4 | 1662/0.4 | 142.9/0.4 | 11.64/0.4 | 50.367 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||||||
C5 | 10 | 10 | 1.524 | Peak|*MPP | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | *870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/ 0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | ||||||||||||
Actual | 836.9/0.5 | 36.29/0.5 | 23.06/0.5 | 828.1/0.5 | 35.53/0.5 | 23.31/0.5 | 10/0.5 | 10/0.5 | 100/0.5 | 1.524/0.5 | 98.948 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t /Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C5 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 | |||||||||||||||
Actual | 810.5/0.5 | 35.15/0.5 | 23.06/0.5 | 1.524/0.5 | 1647/0.5 | 71.44/0.5 | 23.06/0.5 | 50.814 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci /Time | VTEG_Ci /Time | ITEG_Ci /Time | PTEG_Co /Time | VTEG_Co /Time | ITEG_Co /Time | Ts /Time | Tp /Time | Tt /Time | Rt (Ω)/Time | ||||||||||||||
C6 | 10 | 10 | 1.524 | Peak | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | 870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | ||||||||||||
MPP | 884/0.623 | 37.09/0.625 | 23.84/0.621 | 864.5/0.625 | 36.3/0.625 | 23.82/0.625 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.794 | ||||||||||||||||
Actual | 837.1/0.6 | 36.12/0.6 | 23.18/0.6 | 818.5/0.6 | 35.3 /0.6 | 23.17/0.6 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.778 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C6 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 | |||||||||||||||
Actual | 818.5/0.6 | 35.32/0.6 | 23.18/0.6 | 1.524/0.6 | 1656/0.6 | 71.44/0.6 | 23.18/0.6 | 50.549 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω) /Time | ||||||||||||
C7 | 5 | 20 | 0.381 | *MPP | *893.6/0.674 | 18.85/0.674 | 47.39/0.674 | *855.6/0.675 | 18.06/0.675 | 47.39/0.675 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 95.747 | ||||||||||
Actual | 836.7/0.7 | 18.25/0.7 | 45.84/0.7 | 805.3/0.7 | 17.52/0.7 | 45.97/0.7 | 5/0.7 | 20/0.7 | 100/0.7 | 0.381/0.7 | 96.247 | ||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||
C7 | 5 | 20 | 0.381 | Peak | 3719/0.148 | 711.8/0.1 | 47.39/0.674 | 152.4/0.1 | 3743/0.149 | 714.4/0.1 | 47.39/0.674 | 23.874 | |||||||||||||
Actual | 800.6/0.7 | 17.46/0.7 | 45.84/0.7 | 0.381/0.7 | 1637/0.7 | 35.72/0.7 | 45.84/0.7 | 51.112 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C8 | 4 | 25 | 0.24384 | *MPP | *878.6/0.822 | 15.04/0.822 | 58.41/0.823 | *831.8/0.824 | 14.24/0.824 | 58.40/0.824 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 94.673 | |||||||||||
Actual | 836.5/0.8 | 14.68/0.8 | 56.96/0.8 | 791.6/0.8 | 13.89/0.8 | 56.98/0.8 | 4/0.8 | 25/0.8 | 100/0.8 | 0.2438/0.8 | 94.632 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C8 | 4 | 25 | 0.24384 | Peak | 3732/0.149 | 712.4/0.1 | 58.41/0.823 | 152.4/0.1 | 3750/0.149 | 714.4/0.1 | 58.41/0.823 | 23.429 | ||||||||||||||
Actual | 791.3/0.8 | 13.89/0.8 | 56.96/0.8 | 0.2438/0.8 | 1628/0.8 | 28.57/0.8 | 56.96/0.8 | 51.382 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/ Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||||||
C9 | 2 | 50 | 0.06096 | Peak|*MPP | 902.8/0.871 | 7.845/0.867 | 115.2/0.875 | *809.4/0.875 | 7.024/0.875 | 115.2/0.875 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 89.654 | ||||||||||||
Actual | 835.3/0.9 | 7.475/0.9 | 111.8/0.9 | 762.1/0.9 | 6.816/0.9 | 111.8/0.9 | 2.00/0.9 | 50/0.9 | 100/0.9 | 0.06096/0.9 | 91.237 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C9 | 2 | 50 | 0.06096 | Peak | 3750/0.15 | 713.3/0.1 | 115.2/0.875 | 152.4/0.1 | 3758/0.15 | 714.4/0.1 | 115.2/0.875 | 24.023 | |||||||||||||||
Actual | 761.4/0.9 | 6.813/0.9 | 111.8/0.9 | 0.06096/0.9 | 1597/0.9 | 14.29/0.9 | 111.8/0.9 | 52.304 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C10 | 1 | 100 | 0.01524 | Peak|*MPP | 918.4/0.965 | 4.268/0. 949 | 218.8/0.979 | *729.5/0.979 | 3.334/0.979 | 218.8/0.979 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 79.432 | |||||||||||
Actual | 831.2/1 | 3.872/1 | 214.7/1 | 702.4/1 | 3.272/1 | 214.7/1 | 1.00/1 | 100/1 | 100/1 | 0.01524/1 | 84.504 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int /Time | RTEG_Int /Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C10 | 1 | 100 | 0.01524 | Peak | 3754/0.15 | 713.5/0.1 | 218.8/0.979 | 152.4/0.1 | 3761/0.15 | 714.4/0.1 | 218.8/0.979 | 24.419 | ||||||||||||||
Actual | 702.3/1 | 3.272/1 | 214.7/1 | 0.01524/1 | 1533/1 | 7.144/1 | 214.7/1 | 54.220 |
C1 simulation result settings is as follows: TEG_S = Ts = 100; TEG_P = Tp = 1; RL = 152.4 Ω. This means, if the 100 TEGs are connected such that, all 100 of the TEG modules are in series, the total electrical resistance is 152.4 Ω. This is then matched to an electrical load equaling 152.4 Ω for maximum power transfer after the simulation is executed testing all the 10 configurations from C1–C10 (but with focus on C1). The results are exemplified fully in Figure A1 (must refer to the enclosed supplementary file/link for details) and the various C1 parameters captured are summarized in Table 3.
C2 simulation result settings is as follows: TEG_S = Ts = 50; TEG_P = Tp = 2; RL = 38.1 Ω. This means, if the 100 TEG modules are arranged in an array of 50 in series and 2 in parallel, the total electrical resistance is 38.1 Ω. This is then matched to an electrical load equaling 38.1 Ω for maximum power transfer after the simulation is executed testing all the 10 configurations from C1–C10 (with focus now on C2). The results are portrayed fully in Figure A2 (must refer to the enclosed supplementary file/link for details) and the various C2 parameters recorded are summarized in Table 4.
C3 simulation result settings is as follows: TEG_S = Ts = 25; TEG_P = Tp = 4; RL = 9.525 Ω. This means, if the 100 TEG modules are arranged in an array of 25 in series and 4 in parallel, the total electrical resistance is 9.525 Ω. This is then matched to an electrical load equaling 9.525 Ω for maximum power transfer after the simulation is ran testing all 10 configurations from C1–C10 (with focus now on C3). The results are exemplified in full in Figure A3 (must refer to the enclosed supplementary file/link for raw details) and the various C3 parameters recorded are summarized in Table 5.
C4 simulation result settings is as follows: TEG_S = Ts = 20; TEG_P = Tp = 5; RL = 6.096 Ω. This means, if the 100 TEG modules are arranged in an array of 20 in series and 5 in parallel, the total electrical resistance is 6.096 Ω. This is then matched to an electrical load equaling 6.096 Ω for maximum power transfer after the simulation is ran testing all 10 configurations from C1–C10 (with focus now on C4). The results are exemplified fully in Figure A4 (must refer to the enclosed supplementary file/link for raw details) and the various C4 parameters captured are summarized in Table 6.
C5 simulation result settings is as follows: TEG_S = Ts = 10; TEG_P = Tp = 10; RL = 1.524 Ω. This means, if the 100 TEG modules are arranged in an array of 10 in series and 10 in parallel, the total electrical resistance is 1.524 Ω. This is then matched to an electrical load equaling 1.524 Ω for maximum power transfer after the simulation is ran testing all the 10 configurations from C1–C10 (with focus now on C5). The results are exemplified in full in Figure A5 (must refer to the enclosed supplementary file/link for details) and the various C5 parameters measured are summarized in Table 7.
C6 simulation result settings is as follows: TEG_S = Ts = 10; TEG_P = Tp = 10; RL = 1.524 Ω. This means, if the 100 TEG modules are arranged in an array of 10 in series and 10 in parallel, the total electrical resistance is 1.524 Ω. This is then matched to an electrical load equaling 1.524 Ω for maximum power transfer after the simulation is ran testing all 10 configurations from C1–C10 (with focus now on C6). The results are exemplified fully in Figure A6 (must refer to the enclosed supplementary file/link for raw details) and the various C6 parameters recorded are summarized in Table 8.
C7 simulation result settings is as follows: TEG_S = Ts = 5; TEG_P = Tp = 20; RL = 0.381 Ω. This means, if the 100 TEG modules are arranged in an array of 5 in series and 20 in parallel, the total electrical resistance is 0.381 Ω. This is then matched to an electrical load equaling 0.381 Ω for maximum power transfer after the simulation is ran testing all the 10 configurations from C1–C10 (with focus now on C7). The results are exemplified in full in Figure A7 (must refer to the enclosed supplementary file/link for details) and the various C7 parameters measured are summarized in Table 9.
C8 simulation result settings is as follows: TEG_S = Ts = 4; TEG_P = Tp = 25; RL = 0.24384 Ω. This means, if the 100 TEG modules are arranged in an array of 4 in series and 25 in parallel, the total electrical resistance is 0.24384 Ω. This is then matched to an electrical load equaling 0.24384 Ω for maximum power transfer after the simulation is ran testing all 10 configurations from C1–C10 (with focus now on C8). The results are shown fully in Figure A8 (must refer to the enclosed supplementary file/link for details) and the various C8 parameters captured are summarized in Table 10.
C9 simulation result settings is as follows: TEG_S = Ts = 2; TEG_P = Tp = 50; RL = 0.06096 Ω. This means, if the 100 TEG modules are arranged in an array of 2 in series and 50 in parallel, the total electrical resistance is 0.381 Ω. This is then matched to an electrical load equaling 0.06096 Ω for maximum power transfer after the simulation is ran testing all the 10 configurations from C1–C10 (with focus now on C9). The results are depicted in full in Figure A9 (must refer to the enclosed supplementary file/link for details) and the various C9 parameters recorded are summarized in Table 11.
C10 simulation result has the following settings: TEG_S = Ts = 1; TEG_P = Tp = 100; RL = 0.01524 Ω. This means, if the 100 TEG modules are all connected in parallel, the total electrical resistance is 0.01524 Ω. This is then matched to an electrical load equaling 0.01524 Ω for maximum power transfer after the simulation is executed testing all the 10 configurations from C1–C10 (with focus now on C10). The results are shown in full in Figure A10 (must refer to the enclosed supplementary file/link for details) and the various C10 parameters recorded are summarized in Table 12.
Tables 13 and 14 summarized the 100 TEGs 10 unique electrical configurations simulation results, with the detailed and raw simulation results found in the supplementary materials in Appendices A–J (Figures A1–A10). NB: the column parameters/results in each table, correspond to each sub figure parameters/results. That is, the column on TEGs Conv_Pin (W), Vin (V) & Iin (A) results are gotten from their respective appendix sub figures a and c. The column on TEGs Conv_Po (W), Vo (V) & Io (A) results are gotten from their respective appendix sub figures a and d. The column on TEGs series, parallel, total and internal resistance results are gotten from their respective appendix sub figures a and b. The column on TEG(s) internal power (W), voltage (V), current (A) & resistance (Ω) results are gotten from their respective appendix sub figures a and e. The column on TEG(s) ideal power (W), voltage (V) & current (A) results are gotten from their respective appendix sub figures a and f. The columns on TEGs Conv Eff (%) and on TEGs Source Eff (%) are respectively calculated using (PTEG_Co/PTEG_Ci) x 100 and (PTEG_Ci/PTEG_OC) x 100.
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||
C1 | 100 | 1 | 152.4 | Peak | 941.8/0.65 | 243.4/0.246 | 226.6/1 | 704.6/1.031 | 327.7/1.031 | 2.15/1.031 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 74.814 | |
MPP | 908.5/0.175 | 203.5/0.175 | 4.465/0.175 | 386.2/0.246 | 242.6/0.246 | 1.592/0.246 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 42.509 | |||||
Actual | 458.3/0.1 | 116.9/0.1 | 3.92/0.1 | 88.45/0.1 | 116.1/0.1 | 0.7618/0.1 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 19.299 | |||||
C2 | 50 | 2 | 38.1 | Peak|*MPP | 915.3/0.23 | 173.7/0.261 | 5.609/0.174 | *784.7/0.261 | 172.9/0.261 | 4.538/0.261 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 85.731 | |
Actual | 822.3/0.2 | 154.8/0.2 | 5.312/0.2 | 622.6/0.2 | 154/0.2 | 4.042/0.2 | 50/0.2 | 2/0.2 | 100/0.2 | 38.1/0.2 | 75.714 | |||||
C3 | 25 | 4 | 9.525 | Peak|*MPP | 882.3/0.279 | 91.16/0.292 | 9.833/0.268 | *857.5/0.292 | 90.37/0.292 | 9.488/0.292 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.189 | |
Actual | 836.9/0.3 | 90.84/0.3 | 9.213/0.3 | 828.4/0.3 | 88.83/0.3 | 9.326/0.3 | 25/0.3 | 4/0.3 | 100/0.3 | 9.525/0.3 | 98.996 | |||||
C4 | 20 | 5 | 6.096 | Peak |*MPP | 887.4/0.423 | 73.68/0.431 | 12.1/0.419 | *871.6/0.431 | 72.89/0.431 | 11.96/0.431 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 98.219 | |
Actual | 837.1/0.4 | 71.94/0.4 | 11.64/0.4 | 830.3/0.4 | 71.14/0.4 | 11.67/0.4 | 20/0.4 | 5/0.4 | 100/0.4 | 6.096/0.4 | 99.187 | |||||
C5 | 10 | 10 | 1.524 | Peak |*MPP | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | *870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | |
Actual | 836.9/0.5 | 36.29/0.5 | 23.06/0.5 | 828.1/0.5 | 35.53/0.5 | 23.31/0.5 | 10/0.5 | 10/0.5 | 100/0.5 | 1.524/0.5 | 98.948 | |||||
C6 | 10 | 10 | 1.524 | Peak | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | 870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | |
MPP | 884/0.623 | 37.09/0.625 | 23.84/0.621 | 864.5/0.625 | 36.3/0.625 | 23.82/0.625 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.794 | |||||
Actual | 837.1/0.6 | 36.12/0.6 | 23.18/0.6 | 818.5/0.6 | 35.32/0.6 | 23.17/0.6 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.778 | |||||
C7 | 5 | 20 | 0.381 | *MPP | *893.6/0.674 | 18.85/0.674 | 47.39/0.674 | *855.6/0.675 | 18.06/0.675 | 47.39/0.675 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 95.747 | |
Actual | 836.7/0.7 | 18.25/0.7 | 45.84/0.7 | 805.3/0.7 | 17.52/0.7 | 45.97/0.7 | 5/0.7 | 20/0.7 | 100/0.7 | 0.381/0.7 | 96.247 | |||||
C8 | 4 | 25 | 0.24384 | *MPP | *878.6/0.822 | 15.04/0.822 | 58.41/0.823 | *831.8/0.824 | 14.24/0.824 | 58.40/0.824 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 94.673 | |
Actual | 836.5/0.8 | 14.68/0.8 | 56.96/0.8 | 791.6/0.8 | 13.89/0.8 | 56.98/0.8 | 4/0.8 | 25/0.8 | 100/0.8 | 0.2438/0.8 | 94.632 | |||||
C9 | 2 | 50 | 0.06096 | Peak|*MPP | 902.8/0.871 | 7.845/0.867 | 115.2/0.875 | *809.4/0.875 | 7.024/0.875 | 115.2/0.875 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 89.654 | |
Actual | 835.3/0.9 | 7.475/0.9 | 111.8/0.9 | 762.1/0.9 | 6.816/0.9 | 111.8/0.9 | 2.00/0.9 | 50/0.9 | 100/0.9 | 0.06096/0.9 | 91.237 | |||||
C10 | 1 | 100 | 0.01524 | Peak|*MPP | 918.4/0.965 | 4.268/0. 949 | 218.8/0.979 | *729.5/0.979 | 3.334/0.979 | 218.8/0.979 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 79.432 | |
Actual | 831.2/1 | 3.872/1 | 214.7/1 | 702.4/1 | 3.272/1 | 214.7/1 | 1.00/1 | 100/1 | 100/1 | 0.01524/1 | 84.504 |
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||
C1 | 100 | 1 | 152.4 | Peak | 2342/0.1 | 597.5/0.1 | 226.6/1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 226.6/0.1 | 33.127 |
MPP | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 4.28/0.114 | 31.956 | ||||
Actual | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2801/0.1 | 714.4/0.1 | 3.92/0.1 | 16.362 | ||||
C2 | 50 | 2 | 38.1 | Peak | 2581/0.109 | 624.8/0.1 | 5.609/0.174 | 152.4/0.1 | 3043/0.123 | 714.4/0.1 | 5.609/0.174 | 30.079 |
Actual | 1075/0.2 | 202.4/0.2 | 5.312/0.2 | 38.1/0.2 | 1897/0.2 | 357.2/0.2 | 5.312/0.2 | 43.347 | ||||
C3 | 25 | 4 | 9.525 | Peak | 3154/0.129 | 673.5/0.1 | 9.833/0.268 | 152.4/0.1 | 3427/0.138 | 714.4/0.1 | 9.833/0.268 | 25.745 |
Actual | 808.5/0.3 | 87.76/0.3 | 9.213/0.3 | 9.525/0.3 | 1645/0.3 | 178.6/0.3 | 9.213/0.3 | 50.875 | ||||
C4 | 20 | 5 | 6.096 | Peak | 3321/0.134 | 686.5/0.1 | 12.1/0.419 | 152.4/0.1 | 3525/0.141 | 714. 4/0.1 | 12.1/0.419 | 25.174 |
Actual | 825.4/0.4 | 70.93/0.4 | 11.64/0.4 | 6.096/0.4 | 1662/0.4 | 142.9/0.4 | 11.64/0.4 | 50.367 | ||||
C5 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 |
Actual | 810.5/0.5 | 35.15/0.5 | 23.06/0.5 | 1.524/0.5 | 1647/0.5 | 71.44/0.5 | 23.06/0.5 | 50.814 | ||||
C6 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 |
Actual | 818.5/0.6 | 35.32/0.6 | 23.18/0.6 | 1.524/0.6 | 1656/0.6 | 71.44/0.6 | 23.18/0.6 | 50.549 | ||||
C7 | 5 | 20 | 0.381 | Peak | 3719/0.148 | 711.8/0.1 | 47.39/0.674 | 152.4/0.1 | 3743/0.149 | 714.4/0.1 | 47.39/0.674 | 23.874 |
Actual | 800.6/0.7 | 17.46/0.7 | 45.84/0.7 | 0.381/0.7 | 1637/0.7 | 35.72/0.7 | 45.84/0.7 | 51.112 | ||||
C8 | 4 | 25 | 0.24384 | Peak | 3732/0.149 | 712.4/0.1 | 58.41/0.823 | 152.4/0.1 | 3750/0.149 | 714.4/0.1 | 58.41/0.823 | 23.429 |
Actual | 791.3 0.8 | 13.89/0.8 | 56.96/0.8 | 0.2438/0.8 | 1628/0.8 | 28.57/0.8 | 56.96/0.8 | 51.382 | ||||
C9 | 2 | 50 | 0.06096 | Peak | 3750/0.15 | 713.3/0.1 | 115.2/0.875 | 152.4/0.1 | 3758/0.15 | 714.4/0.1 | 115.2/0.875 | 24.023 |
Actual | 761.4/0.9 | 6.813/0.9 | 111.8/0.9 | 0.06096/0.9 | 1597/0.9 | 14.29/0.9 | 111.8/0.9 | 52.304 | ||||
C10 | 1 | 100 | 0.01524 | Peak | 3754/0.15 | 713.5/0.1 | 218.8/0.979 | 152.4/0.1 | 3761/0.15 | 714.4/0.1 | 218.8/0.979 | 24.419 |
Actual | 702.3/1.0 | 3.272/1.0 | 214.7/1.0 | 0.01524/1.0 | 1533/1.0 | 7.144/1.0 | 214.7/1.0 | 54.220 | ||||
*Note: where applicable in the tables, *MPP means MPP is also Peak. |
It should also be noted that, the points named and highlighted A–V on Figure A1, is also applicable to the same unnamed points/positions on Figures A2–A10. However, the only difference is, the value each point has on their respective figures is now different due to their respective configurations. Furthermore, the points named J, K, L, O, P/R, T and U/V; will have different positions (but the same designation and meaning) as well as different values depending on the respective simulation configurations. Finally, the points named W–Z on Figures A1–A10 have the same meaning on their respective figures, though the only difference is their position and value, since the simulation results have different configurations. The meaning of each point and results interpretation are discussed in Section 4.
Prior to discussing the simulation results (see supplementary file/link), it is prudent to first clarify the various simulation parameters nomenclature used as well as the meaning and significance of the various points highlighted and labeled A–Z. The parameter Rt is the TEG(s) total resistance. This parameter is also electrically the same as the TEGs internal resistance termed TEGRtint in the simulation and RTEG_Int in Table 14. Furthermore, at maximum power point (MPP), parameter Rt is theoretically equal to RL—which is the variable load resistor in the simulation. The TEGs in series denoted TEG_S, is the same as the designation Ts in the simulation. Likewise, the TEGs in parallel denoted TEG_P, is the same as the designation Tp. In the simulation, Tt is the total TEGs quantity as per a configuration. NB, Tt is different from Rt—the latter defines the TEGs total resistance, whereas the former defines the total TEG amount (quantity) used. The TEGs output voltage denoted (Vo) in the mathematical analysis and in Figure 1, is the same as the TEGs converter input voltage designated Vin in the simulation and VTEG_Ci in Table 13. The same applies to the TEGs output current (I), being the same as the TEGs converter input current designated Iin in the simulation and ITEG_Ci in Table 13. Furthermore, the TEGs output power (Po), is the same as the TEGs converter input power designated Pin in the simulation and PTEG_Ci in Table 13. The TEGs converter output voltage designated Vout in the simulation and VTEG_Co in Table 13, are the same as the load voltage. The same applies to the TEGs converter output current designated Iout in the simulation and ITEG_Co in Table 13, which are the same as the load current. Furthermore, the TEGs converter output power designated Pout in the simulation and PTEG_Co in Table 13, are the same as the load power. It should be noted that the same current that flows through the TEGs Rt, is the same as the current that flows through RL—since Rt and RL are electrically in series. The TEGs internal power PTEG_Int, voltage VTEG_Int, current ITEG_Int and resistance RTEG_Int as denoted in Table 14, are respectively the same as PTEGRtint, VTEGRtint, ITEGRtint and TEGRtint as in the simulation and Figure 1. The TEGs ideal power PTEG_OC, voltage VTEG_OC and current ITEG_OC as denoted in Table 14, are respectively the same as TEGPocM, TEGVoc and TEGIoc as shown in the simulation and Figure 1. The simulated measurement in Tables 13 and 14, has three kinds of measurement named Peak, MPP and Actual. The peak value is the highest measurement recorded anywhere and at any time (from 0−1.1) in the simulation. For example, 941.8/0.65 for C1 at corresponding 0.1 simulation time in Table 13, means we recorded peak or maximum TEGs output power of 941.8 W at simulation time of 0.65. However, in Table 13 for C1 at corresponding 0.1 simulation time, we recorded respective peak voltage and current as 243.4/0.246 and 226.6/1. As can be seen, the peak power is not the product of the peak voltage and current at C1, because the peak power, voltage and current can occur at different simulation times (0.65, 0.246 and 1.0 in this case), even though the TEGs configuration under testing was C1 that corresponds to simulation time 0.1. The MPP value is the measurement recorded at MPP at the same simulation time instant (e.g., 0.175), which however doesn't correspond to the TEGs configuration number (e.g., C1). NB: TEGs configuration number C1−C10, correspond to simulation time 0.1−1.0. For example: Table 13 in configuration C1 at corresponding 0.1 simulation time, we recorded respective MPP power, voltage and current as 908.5/0.175,203.5/0.175 and 4.465/0.175. As apparent, the MPP power, voltage and current occurred at the same simulation time of 0.175, consequently the MPP power is a product of the MPP voltage and current. However, the simulation time of 0.175 when the MPP parameters values were measured, don't correspond to the TEGs configuration number (C1) corresponding simulation time of 0.1 in this case. The actual value (the research focus) is the measurement recorded at exactly the same simulation time (e.g., 0.1) which must correspond to its respective TEGs configuration (e.g., C1) in this case. For example, Table 13 in TEGs configuration C1 at corresponding 0.1 simulation time, recorded respective actual power, voltage and current are 458.3/0.1,116.9/0.1 and 3.92/0.1. As evident, the actual power is the product of the actual voltage and current—which all 3 occurred at the same simulation time of 0.1, which also corresponds to the TEGs C1 configuration. It should be noted that, the i) Actual, ii) MPP and iii) Peak simulated measurement types as defined/described in the context of this research article, are merely reasonable terminologies used to define and differentiate the three types of simulated measurements for the sake of ease of understanding and explaining. NB: there are few instances (e.g., C1) where the Peak as well as MPP measurements don't accurately conforms to their definitions used here—that is, the Peak readings at times, may obey the MPP definition and also the MPP readings can be Peak readings but do not obeys the Peak definition sometimes.
The simulation results highlighted points of interest, labeled A−Z in the supplementary materials (see link at the end), where applicable in Figure 1, Figures A1−A10 and also in Tables 3−14, are clearly defined and explained in details as follows:
Point A: This is the TEGs ideal power (W), voltage (V) and current (A) parameters; respectively (TEGPocM = PTEG_OC, TEGVoc = VTEG_OC and TEGIoc = ITEG_OC). TEGs ideal parameters is the maximum power, voltage and current that can be produced assuming TEGs has no internal source resistance; that is Rt = 0. This means all the power, voltage, current produced will be delivered to the load, which in reality is not the case due to Rt. That is, TEG ideal power is the sum of the TEG internal resistance power (power lost as heat due to Rt and Joule or Ohmic heating) and TEG output power (power delivered to the load). This is an interesting parameter, as it reveals i) the maximum power that TEG(s) can produce and ii) the effects of TEG(s) total internal source resistance Rt—the smaller the Rt, the more the TEGs output power. This parameter is summarised in Table 14 and is depicted in Figure 1 as well as in Figures A1−A10.
Point B: This is the series (Ts = TEG_S) and parallel (Tp = TEG_P) TEG(s). They are used to choose the number (infinite) of TEGs to be connected in series and or parallel. Connecting more TEGs in series (Ts) increases the TEGs output voltage and connecting more in parallel (Tp) increases the TEGs output current. However, connecting more TEGs in series also increases the TEGs internal resistance (NB: TEGRtint = Rt), which as a result inefficiently affects (decreases) the TEGs output current and power, since the increase in TEGRtint increases the voltage drop over it, consequently increases the power loss (P = VTEGRtint2/TEGRtint). However, connecting more TEGs in parallel also decreases the TEGs internal resistance (TEGRtint = Rt), which as a result affects (decreases) the TEGs output voltage and power, since the decrease in TEGRtint decreases the voltage drop; however, it increases the output current which consequently increases the power loss (P = ITEGRtint2TEGRtint) due to Joule or Ohmic heating. It should be noted that a TEG akin a battery, is a voltage source and a good or ideal voltage source is one with respectively very little or no internal source resistance, which is practically impossible. Therefore, a balance has to be made and one way is connecting the TEGs in series and in parallel to optimize both the TEGs outputs voltage and current. However, it's prudent to first ascertain RL to ensure whatever configuration of Ts and Tp are used, gives a TEGRtint or Rt that matches RL for efficient direct maximum power transfer—without too much power conditioning/management required. Of course in practice, a boost DC-DC converter with energy management is paramount for reliable performance should the load changes; however, always first matching Rt = RL will boost the system efficiency, besides just power output.
Point C: This is the TEGs total internal resistance (TEGRtint = Rt) and the most vital TEGs electrical parameter. Rt is the total electrical resistance resulting from connecting multiple Ts and or Tp. When Rt = RL, maximum power shall be transferred from the TEGs to the load, though TEGs maximum power don't exactly happens at Rt = RL.
Point D: This is the TEGs total internal voltage (VTEGRtint), current (ITEGRtint) and power (PTEGRtint) as a result of the TEGs total internal resistance TEGRtint or Rt. Without Rt, all the power generated by the TEGs, can be delivered to the load. Therefore, by minimizing Rt, the TEGs output power and delivery to the load, can be maximally produced and efficiently delivered respectively.
Point E: This simply illustrates the product of Ts and Tp to give Tt—which is the total number of TEGs used. Tt (TEGs total amount) is different from Rt (TEGs total resistance).
Point F: This is the actual TEGs output or better, generated power (Pin), voltage (Vin) and current (Iin) as designated in the simulation, which is the same as the TEGs converter input power (PTEG_Ci), voltage (VTEG_Ci) and current (ITEG_Ci) as designated in Table 13. NB: It will be the output power, voltage and current delivered directly to the load (if there wasn't a boost converter) and it is practically the difference between the TEGs ideal and internal parameters. That is, Pin = TEGPocM − PTEGRtint; Vin = TEGVoc − VTEGRtint and Iin = TEGIoc − ITEGRtint.
Point G: This is the TEGs electrical load resistance (RL). Without the boost converter (interleave boost converter for this study) in between, RL connects directly to the TEGs output (practically to Rt or TEGRtint). For maximum power transfer, with or without the boost converter, RL should equals Rt, but in reality it is actually not the case for TEG(s) due to non-linearity. In our simulations, usually RL as per a specific TEGs configuration (e.g., C1) must first be determined and set (e.g., RL = 152.4 Ω for C1) and the simulation executed, during which the values of Ts, Tp, Tt and Rt are observed as they automatically change and at the corresponding simulation time of 0.1 in this case; Ts will = ~100, Tp = ~1, Tt = ~100 and Rt = ~152.4 Ω which theoretically necessitate maximum power transfer to be attained.
Point H: This is the TEGs boosted output with maximum power point tracking (MPPT) power (Pout), voltage (Vout) and current (Iout) delivered directly to the load RL as designated in the simulation —which is the same as the TEGs boost converter/MPPT output power (PTEG_Co), voltage (VTEG_Co) and current (ITEG_Co) as denoted in Table 13. NB: the MPPT setting is the same for all 10 configurations; hence, its effects is the same for all and thus not discussed.
Point I: This is the simulation time (from 0 to 1.1 or better from 0.1 to 1) which should correspond to the respective TEGs configurations of C1−C10 and it's used when measurements are recorded. That is, once at simulation time 0.1 with RL = 152.4 Ω, the TEGs configuration will automatically be exactly at C1 in which Ts = ~100, Tp = ~1, Tt = ~100 and Rt = ~152.4 Ω; at simulation time 0.2 with RL = 38.1 Ω, the TEGs configuration will automatically be exactly at C2 whereby Ts = ~50, Tp = ~2, Tt = ~100 and Rt = ~38.1 Ω and so forth till simulation time 1.0, corresponding to C10.
Point J: This is the dynamic Rt value with respect to each TEGs configuration C1−C10. Mindful that the TEGs Rt value and position will respectively change downwards and to the right as the simulation progresses from simulation time 0.1 to 1.0 for C1 to C10 respectively.
Point K: This is the Tt (i.e. product of Ts and Tp) value with respect to each TEGs configuration C1−C10. It should be noted that irrespective of the configuration, the Tt value will approximately stay the same (i.e., Tt = ~100) while the position will change to the right as the simulation progresses from simulation time 0.1 for C1 to 1.0 for C10. However, at non C1−C10 values, Tt will be at maximum of ~112.5 for this particular study example.
Point L: This is the same as Point I; however, the only difference is this keeps tracks of the simulation time on the graphs whereas, Point I keeps track of GUI simulation time.
Point M: This shows cursors 1 and 2 measurements value and the simulation time the measurements were made. At certain instances, these cursors 1 and 2 measurements parameters, values and simulation times will vary depending on the investigation made.
Point N: This simply displays the measurement statistics. However, of interest here is the peak or maximum value and the corresponding simulation times of occurrence.
Point O: This indicates the simulated TEGs converter input power actual measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. This is the simulated TEGs output power measurement critical research tests point of interest.
Point P: This indicates the simulated TEGs converter input power MPP measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. This is the simulated TEGs output power measurement first control research point of interest.
Point Q: This indicates the simulated TEGs output voltage peak measurement.
Point R: This indicates the simulated TEGs converter input power peak measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. This is the simulated TEGs output power measurement second control research interest point.
Point S: This indicates the simulated TEGs output current peak measurement.
Point T: This indicates the simulated TEGs converter output power actual measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. This is the simulated TEGs boost converter load (terminal) power measurement critical research test point of interest. Please note carefully the difference between Point T and Point O.
Point U: This indicates the simulated TEGs converter output power MPP measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. This is the simulated TEGs boost converter load (terminal) power measurement first control research interest point. Please note carefully the difference between Point U and Point P.
Point V: This indicates the simulated TEGs converter output power peak measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. This is the simulated TEGs boost converter load (terminal) power measurement second control research interest point. Please note carefully the difference between Point V and Point R.
NB: U|V means the output power measurement could either be considered MPP or Peak measurement.
Finally, the following four points (W−Z) of interest apply to Appendices A−J (that is, supplementary material Figures A1−A10 sub-figures a, e and f only) and are defined and explained as follows:
Point W: This marks the simulated TEGs internal resistance power (PTEGRtint) peak measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. PTEGRtint is a very vital parameter, as it demonstrates the effects of the source internal resistance (TEGRtint) which is very crucial for a voltage source. The more the TEGRtint, the more the generated TEGs power will be dissipated as heat, causing TEGs to be very inefficient.
Point X: This signifies the simulated TEGs internal resistance power (PTEGRtint) actual measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. At C1, W equals X, as the PTEGRtint measurement is at maximum corresponding to C1. However, X value will always be less than W value and X will decrease from left to right for subsequent C2−C10 configurations tests, corresponding to simulation times 0.2−1.0.
Point Y: This denotes the simulated TEGs ideal power (TEGPocM or PTEG_OC) peak measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10. TEGPocM is a very vital parameter, as it demonstrates the effects of the source internal resistance TEGRtint, which is very crucial for a voltage source. Without TEGRtint, all the generated TEGs power will theoretically be delivered to the load, causing the TEGs to be very efficient. However, this is hardly the case in practice, as the thermoelectric elements used have intrinsic resistance and therefore minimising TEGRtint will enhance TEGs performance.
Point Z: This signifies the simulated TEGs ideal power (TEGPocM or PTEG_OC) actual measurements value at the simulation times 0.1 to 1.0 corresponding to C1 to C10—meaning, Z value will always be less than Y value and Z will decrease from left to right for subsequent C2−C10 configurations tests, corresponding to simulation times 0.2−1. NB: subtracting PTEGRtint from TEGPocM will give the TEGs real output or load power (TEGPo).
The simulated TEGs respective configurations results presented in Section 3 are respectively engaged now as follows:
In TEGs C1 as displayed in Figure A1a, RL is first calculated and set to 152.4 Ω and the simulation ran while noticing the Ts, Tp, Tt and Rt values changing. At exactly 0.1 simulation time; Ts, Tp, Tt and Rt should respectively exactly read 100, 1,100,152.4 Ω as shown in Figures A1a and A1b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A1c and A1d, as well as the TEGs internal power, voltage, current and resistance pictured in Figure A1e and finally the TEGs ideal power, voltage and current depicted in Figure A1f. These results are summarized in Tables 3, 13 and 14; including also the TEGs boost converter efficiency (calculated as: (PTEG_Co/PTEG_Ci) x 100) and the TEGs source efficiency (calculated as: (PTEG_Ci/PTEG_OC) x 100). NB: the TEGs boost converter input and output powers MPP respectively occurred but at 0.175 and 0.246 simulation times instead of at 0.1—corresponding to TEGs configuration C1. Furthermore, proceeding the MPP value and from simulation time 0.27, the TEGs internal resistance voltage and current as shown in Figure A1e, the TEGs ideal power and current as shown in Figure A1f and the TEGs converter Pin and Iin as shown in Figure A1c, dropped to around zero until after 0.6 simulation time. These TEGs parameters dynamics, symbolizes the effect if the TEGs source internal resistance TEGRtint or Rt is connected to an electrical load RL of 152.4 Ω and then matched and mismatched.
In TEGs C2 as displayed in Figure A2a, RL is first computed and set to 38.1 Ω and the simulation executed while observing the Ts, Tp, Tt and Rt values changing. At exactly 0.2 simulation time; Ts, Tp, Tt and Rt should exactly read 50, 2,100, 38.1 Ω respectively as shown in Figures A2a and A2b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A2c and A2d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A2e and finally the TEGs ideal power, voltage and current depicted in Figure A2f. These results are summarized in Tables 4, 13 and 14 including the TEGs boost converter efficiency and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.23 and 0.261 simulation times instead of 0.2—corresponding to TEGs configuration C2. The TEGs converter Pin, Vin and Iin are shown in Figure A2c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A2d, the TEGs internal resistance, power, voltage and current are shown in Figure A2e and the TEGs ideal power, voltage and current are depicted in Figure A2f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to a load RL of 38.1 Ω and then matched and mismatched.
In TEGs C3 as shown in Figure A3a, RL is first calculated and set to 9.525 Ω and the simulation executed while observing the Ts, Tp, Tt and Rt values changing. At exactly 0.3 simulation time; Ts, Tp, Tt and Rt should exactly respectively read 25, 4,100, 9.525 Ω as shown in Figures A3a and A3b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A3c and A3d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A3e and finally the TEGs ideal power, voltage and current depicted in Figure A3f. These results are summarized in Tables 5, 13 and 14 as well as including the TEGs boost converter efficiency (NB: this for C3 gave 101.74% in the dynamic resistance simulation, which was investigated to be an anomaly only for C3 and likely caused by transients/timing, since C3 Rt wasn't exactly 9.525 Ω —this was checked using static resistance simulation and it correctly gave 98.996%) and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.279 and 0.292 simulation times instead of 0.3, corresponding to TEGs configuration C3. The TEGs converter Pin, Vin and Iin are shown in Figure A3c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A3d, the TEGs internal resistance, power, voltage and current are shown in Figure A3e and the TEGs ideal power, voltage and current are depicted in Figure A3f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to a load RL of 9.525 Ω and then matched and mismatched.
In TEGs C4 as shown in Figure A4a, RL is first computed and set to 6.096 Ω and the simulation executed while watching the Ts, Tp, Tt and Rt values changing. At exactly 0.4 simulation time; Ts, Tp, Tt and Rt should respectively exactly read 20, 5,100, 6.096 Ω as shown in Figures A4a and A4b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A4c and A4d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A4e and finally the TEGs ideal power, voltage and current depicted in Figure A4f. These results are summarized in Tables 6, 13 and 14 including the TEGs boost converter efficiency and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.423 and 0.431 simulation times instead of 0.4—corresponding to TEGs configuration C4. The TEGs converter Pin, Vin and Iin are shown in Figure A4c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A4d, the TEGs internal resistance, power, voltage and current are shown in Figure A4e and the TEGs ideal power, voltage and current are depicted in Figure A4f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to a load RL of 6.096 Ω and then matched and mismatched.
In TEGs C5 as shown in Figure A5a, RL is first computed and set to 1.524 Ω and the simulation executed while watching the Ts, Tp, Tt and Rt values changing. At exactly 0.5 simulation time; Ts, Tp, Tt and Rt should exactly respectively read 10, 10,100, 1.524 Ω as shown in Figures A5a and A5b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A5c and A5d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A5e and finally the TEGs ideal power, voltage and current depicted in Figure A5f. These results are summarized in Tables 7, 13 and 14 including the TEGs boost converter efficiency and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.475 and 0.478 simulation times instead of 0.5—corresponding to TEGs configuration C5. The TEGs converter Pin, Vin and Iin are shown in Figure A5c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A5d, the TEGs internal resistance, power, voltage and current are shown in Figure A5e and the TEGs ideal power, voltage and current are depicted in Figure A5f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to a load RL of 1.524 Ω and then matched and mismatched.
In TEGs C6 as shown in Figure A6a, RL is first calculated and set to 1.524 Ω and the simulation executed while noticing the Ts, Tp, Tt and Rt values changing. At exactly 0.6 simulation time; Ts, Tp, Tt and Rt should respectively exactly read 10, 10,100, 1.524 Ω as shown in Figures A6a and A6b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A6c and A6d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A6e and finally the TEGs ideal power, voltage and current depicted in Figure A6f. These results are summarized in Tables 8, 13 and 14 including the TEGs boost converter efficiency and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.623 and 0.625 simulation times instead of 0.6—corresponding to TEGs configuration C6. The TEGs converter Pin, Vin and Iin are shown in Figure A6c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A6d, the TEGs internal resistance, power, voltage and current are shown in Figure A6e and the TEGs ideal power, voltage and current are depicted in Figure A6f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to a load RL of 1.524 Ω and then matched and mismatched.
In TEGs C7 as shown in Figure A7a, RL is first computed and set to 0.381 Ω and the simulation executed while observing the Ts, Tp, Tt and Rt values changing. At exactly 0.7 simulation time; Ts, Tp, Tt and Rt should exactly respectively read 5, 20,100, 0.381 Ω as shown in Figures A7a and A7b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A7c and A7d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A7e and finally the TEGs ideal power, voltage and current depicted in Figure A7f. These results are summarized in Tables 9, 13 and 14 including the TEGs boost converter efficiency and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.674 and 0.675 simulation times instead of 0.7—corresponding to TEGs configuration C7. The TEGs converter Pin, Vin and Iin are shown in Figure A7c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A7d, the TEGs internal resistance, power, voltage and current are shown in Figure A7e and the TEGs ideal power, voltage and current are depicted in Figure A7f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to a load RL of 0.381 Ω and then matched and mismatched.
In TEGs C8 as shown in Figure 8a, RL is first computed and set to 0.24384 Ω and the simulation executed while watching the Ts, Tp, Tt and Rt values changing. At exactly 0.8 simulation time; Ts, Tp, Tt and Rt should respectively exactly read 4, 25,100, 0.24384 Ω as shown in Figures A8a and A8b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A8c and A8d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A8e and finally the TEGs ideal power, voltage and current depicted in Figure A8f. These results are summarized in Tables 10, 13 and 14; having also the TEGs boost converter efficiency and TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.822 and 0.824 simulation times instead of 0.8—corresponding to TEGs configuration C8. The TEGs converter Pin, Vin and Iin are shown in Figure 8c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A8d, the TEGs internal resistance, power, voltage and current are shown in Figure A8e and the TEGs ideal power, voltage and current are depicted in Figure A8f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to load RL of 0.24384 Ω and then matched and mismatched.
In TEGs C9 as shown in Figure A9a, RL is first computed and set to 0.06096 Ω and the simulation executed while noticing the Ts, Tp, Tt and Rt values changing. At exactly 0.9 simulation time; Ts, Tp, Tt and Rt should exactly respectively read 2, 50,100, 0.06096 Ω as shown in Figures A9a and A9b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A9c and A9d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A9e and finally the TEGs ideal power, voltage and current depicted in Figure A9f. These results are summarized in Tables 11, 13 and 14 including the TEGs boost converter efficiency and the TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.871 and 0.875 simulation times instead of 0.9—corresponding to TEGs C9. The TEGs converter Pin, Vin and Iin are shown in Figure A9c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A9d, the TEGs internal resistance, power, voltage and current are shown in Figure A9e and the TEGs ideal power, voltage and current are depicted in Figure A9f. These TEGs parameters dynamics symbolizes the effect if the TEGs TEGRtint or Rt is connected to load RL of 0.06096 Ω and then matched and mismatched.
In TEGs C10 as shown in Figure 10a, RL is first computed and set to 0.01524 Ω and the simulation executed while noticing the Ts, Tp, Tt and Rt values changing. At exactly 1.0 simulation time; Ts, Tp, Tt and Rt should exactly respectively read 1,100,100, 0.01524 Ω as shown in Figures A10a and A10b. The TEGs converter associated input and output powers, voltages and currents are portrayed in Figures A10c and A10d, as well as the TEGs internal power, voltage, current and resistance pictured in Figures A10e and finally the TEGs ideal power, voltage and current depicted in Figure A10f. These results are summarized in Tables 12, 13 and 14; having also the TEGs boost converter efficiency and TEGs source efficiency. NB: the TEGs boost converter Pin and Pout MPP respectively occurred but at 0.965 and 0.979 simulation times instead of 1.0, corresponding to TEGs configuration C10. The TEGs converter Pin, Vin and Iin are shown in Figure A10c, the TEGs converter Pout, Vout and Iout are portrayed in Figure A10d, the TEGs internal resistance, power, voltage and current are shown in Figure A10e and the TEGs ideal power, voltage and current are shown in Figure A10f. These TEGs parameters dynamics symbolize the effect if the TEGs TEGRtint or Rt is connected to load RL of 0.01524 Ω and then matched and mismatched.
Our TEGs simulated model and results were scientifically validated where possible in fairly two ways, as follows:
With this approach, a simple TEGs total resistance (Rt), power, voltage, current and TEGs Ts, Tp and Tt comparisons were done between the calculations in Table 2 with their corresponding simulated numeric and graphical results displayed in Figures A1−A10 as well as Tables 3−12 and finally the summary in Tables 13 and 14. These results closely correlated each other, confirming the results validity of the different TEGs configurations, with focus on the source to load resistance matching and maximum power transfer. NB: any other parameters or dynamics or factors even if important, are not the focus of this research and therefore were simply treated as constants/ideal parameters throughout this study and not taken into considerations; as a result, their effects were not also discussed.
The next phase of our research is to do a practical implementation, which as can been seen would be extensive, considering the quantity of TEGs involved and the various configurations (10) as well as finding actual TEGs with the exact simulated specifications. Furthermore, vital practical aspects are to be considered and though they'll influence the practical results; notwithstanding, they'll still be treated as constants and will thus have no effect on the actual TEGs source to load maximum power transfer comparisons of the different TEGs configurations—which is the main dynamic focus of this study. So, it's reasonable to say in as much a practical implementation is necessary, it's not critical for use to validate this research aims, as the basic electrical maths and simulation results validate it. Nevertheless, various past studies results in [21,22,23,24,25,26,27,28,29,30] relevant to our study were analysed and their findings where applicable to our study were compared and engaged as follows. In [21], a 500 W TEG system was practically designed using 96–100 TEG modules to convert geothermal heat to power. The number of thermocouples n used in each TEG was 127. These are the only two similar parameters found in our study. They reported that 500 W of output power was attained when the temperature difference was 200 ℃. Our temperature difference is 150 ℃. What is interesting and the more reason our study is relevant is the type of TEGs configuration used—they didn't mention it, perhaps had they used the right optimal TEG configuration with respect to the given electrical load, the generated power would've been more, hence the aim for our study. It's worth mentioning that 500 W is closest to our configuration C1 (the least optimal configuration) which produces ~ 458 W. We're not sure whether this was the configuration they used as details were not given—it would've been useful had all the technical details used were given in their study for us to compare and benchmark our study with. Similarly in [22], a 1000 W TEG system was practically designed using 600 TEG modules to convert geothermal heat to power. The number of thermocouples n used in each TEG was 127—this is the only technical parameter the same as ours. The temperature difference was 120 ℃ and lower than ours. The configuration used was not mentioned; however, they indicated that with more temperature difference, up to 2 kW of power could be attained. Furthermore, they also highlighted that it's cheaper to generate the same DC power using TEGs, compared to using solar system. In [23], a 1 kW TEG power system to convert geothermal heat to electricity was modeled. The number of thermocouples n used in each TEG was 127—this is the only technical parameter the same as ours. The temperature difference was 200 K or 200 ℃ (note, temperature difference in kelvin is the same as ℃). The exact configuration wasn't mentioned besides that it was an array of 10−50 of about 550 TEGs (it's worth mentioning that they didn't used TEG but TEC modules—both can be used interchangeably, though TEC if used as TEG, its hot-side maximum temperature should be below 200 ℃). Other studies of interest that involved use of multiple TEGs to generate power, though with a different approach, aims and specifications as ours, include; in [24], whereby the use of TEGs to recover waste heat from automobile exhaust with focus on temperature distribution, TEG module surface area and the cold-side cooling fluid (air and water) were examined. In [25], 20 TEGs in two series pairs of 10 each were used to recover heat in diesel engines with focus on temperature—with the pair of TEGs exposed to hotter temperature generating more power compared to the pair of TEGs exposed to less hot temperature. Various car heat recovery systems with heat pipes were examined in [26], whereby 38 high temperature TEGs were used to generate 750 W of power in a BMW car, another TEG array (quantity not mentioned) in Ford car was used to generate 400 W, followed by a Renault car with a TEG array (quantity not mentioned) to produce 1 kW and finally a Honda consisting of 32 TEGs to generate 500 W. Studied in [27], a 750 W TEG system of different thermocouple materials produced different results with more power/current generated with higher temperature on TEG hot-side. Electro-thermal dynamics of series-parallel TEGs was modeled and experimented in [28] and the results showed that the electrical interconnections of TEGs with respect to an electrical load, has significant effect on their power output—supporting our study. Covered in [29] was optimising the number of TEGs used and the distribution pattern for waste heat recovery, in which the number of TEGs (306) in a 18 x 17 array were assessed and their findings portrayed that the central TEGs generate more power compared to peripheral TEGs (which have less hot temperature exposure) suggesting that more TEGs may not necessarily increase the output power or efficiency if poorly exposed to a hot temperature. Investigated in [30], is the mismatched when 80 series/parallel connected TEGs are used for heat recovery—it revealed that connecting all TEGs in series is less efficient relative to the TEGs connected in groups of two or four as exemplified in Figure 3, which affirms why our C1 configuration is less efficient compared to the other configurations. This is because connecting TEGs in series increases resistance Rt which is bad for a voltage source and therefore causes proportional power loss as heat. In [30], it is also stated that source and load mismatch affects TEGs power output and a particular interconnection choice depends on TEGs load—which supports our findings that the electrical load value must first be determined. Our TEG parameters specifications were gotten from datasets found in [20] and TEG modules TG12-4 and TGM-127-1.4-2.5. datasheets. Thus, using our unique model, various optimal TEGs configuration analysis of any quantity and array, can be studied to choose an optimal connection whose source resistance matches the load to ensure maximum power is transferred. This concludes our validation and gives a rough practical perspective considering other factors/dynamics not covered in our study. Furthermore, not every configuration aspect of our study was validated due to lack of experimented data or similar studies (which indicates uniqueness of our study); however, the few aspects validated gave promising results and our next study is to conduct several experiments for all the 10 configurations and correlate our results further.
We've developed and fairly validated a basic simulated TEGs model with supporting maths and further simulated 100 TEGs in 10 unique electrical configurations C1−C10 to determine TEGs optimal configuration. It was realised that C1 at corresponding simulation time of 0.1 has the most TEG boost converter input and output voltages of ~ 116 V but worst source resistance (TEGRtint = Rt = 152.4 Ω), worst TEG converter input and output powers of ~ 458 W and 88 W respectively and worst TEG boost converter and source efficiencies of ~ 19% and ~ 16% respectively. This is due to most of the TEGs generated power wasted in the very high TEGRtint. C3 with TEGRtint = Rt = 9.525 Ω and C4 with TEGRtint = Rt = 6.096 Ω, gave approximately 99% TEG boost converter efficiency and more than 50 % source efficiency. C3 and C4 configurations are recommended where multiple TEGs are to be connected in series to increase the output voltage. C5 and C6 are of interests, as their TEGRtint = Rt = R = 1.524 Ω, which is exactly the R of the unit TEG used—meaning C5 or C6 is an even (symmetrical) electrical configuration, which simply changes a unit TEG to a bigger TEG with approximate manufacturer R value but now with more voltage, current and power capabilities. Also, C5 and C6 have more or less the same performance though with slight differences. C5 has a TEG boost converter efficiency of ~ 98.9% whereas C6 has a TEG boost converter efficiency of ~ 97.8%. Their respective source efficiencies are ~ 50.8% and ~ 50.5%. Though C5 and C6 have been presented here differently and with slight performance differences, it's just for theoretical explanation, as in practice C5 = C6 with the same setup and results. Where both optimal high output voltage and current are paramount, C5 or C6 is recommended. C7 and C8 with respective TEGRtint = Rt = 0.381 Ω and 0.024384 Ω, respectively gave a TEG boost converter efficiency of ~ 96.2% and ~ 94.6%; whereas C7 and C8 have a TEG source efficiency of ~ 51.11% and ~ 51.38% respectively. These C7 and C8 configurations are advisable where multiple TEGs are to be connected in parallel to increase the TEGs output current. Finally, C10 with TEGRtint = Rt = 0.01524 Ω gave the most output current with the highest TEGs source efficiency of 54.3%; however, it has a TEG boost converter efficiency of ~ 84.5%. It should be noted that C10 Rt is approximately equal to the TEG p-n thermoelectric element resistance r = 0.012 Ω; therefore, operating TEGs at this configuration will not only limit its practical performance, but will also affects it longevity due to the very high current and consequent Joule heating involved. C2 and C9 have average performances, though just respectively better than C1 and C10. It's worth mentioning that the TEGs boost converter MPP output power, voltage and current simulation times are all synchronized unlike the TEGs boost converter MPP input power, voltage and current simulation times, which are different except in C7 and C8. The TEGs boost converter and MPPT removed some ripples and stabilized the output.
In all, this paper main scientific merits/highlights/insights are summarised as follows:
We've developed a simple tool using Matlab and Simulink that can be employed to easily calculate, simulate and study any single-stage TEGs amount resistance matching and be it in any series/parallel configurations/connections.
Furthermore, any TEG amounts and in any different electrical configurations, can be all simulated concurrently—meaning, any TEG quantity for example 1600,750,505,330, 99, 72, 60, 18 etc and in each case their different electrical configurations (which are simply factors of each of those numbers), can be all simulated at once. We've theoretically demonstrated it herein using 100 TEGs in 10 different electrical configurations.
These different TEGs configurations total output resistance can be determined and can be matched to an electrical load (which we can also vary its resistance value in real-time) to determine the optimal TEGs configuration and performance with respect to the electrical load resistance—which is very key to know when doing a TEG(s) design.
Our work also shows the power loss and voltage drop as well as Ohmic/Joule heating current that occur in the TEGs and when many TEGs are used, as well as when the electrical configurations are changed with respect to a particular electrical load. Our TEGs model also shows that certain electrical configurations give better power loss and therefore more power output and most importantly better output power efficiency.
Finally, we show that using many TEGs of the same model and in even electrical configuration, gives better results.
Renewable energy is currently gaining traction to augment countries national grids and for personal use. As an alternative, we advance the case for thermoelectricity with focus on Rt when using multiple TEGs to increase the generated DC power. A modest mathematical presentation for multiple TEGs was expressed, proceeded by modeling with Matlab/Simulink. The TEGs model was used to simulate and determine 100 TEGs performance in 10 different electrical configurations. In sum, while it's good and tempting to functionally connect many TEGs in series and or in parallel to respectively increase the voltage and current outputs, it's better to understand their electrical dynamics as well as their practical optimal operation points/limits and best to determine which TEGs electrical configurations can give optimal performance with respect to a particular load. In light of this, this research findings conclude that the TEG load resistance RL must first be established, from which different TEGs configurations can be experimented to compute different values of Rt and to determine a TEGs configuration with an optimal or suitable source resistance Rt that matches the load resistance to ensure maximum power is transferred to it and efficiently. However, in as much Rt should equals RL to ensure transfer of maximum power, from our simulation results, TEG(s) maximum power is not transferred at exactly Rt = RL but at slightly more or less due to non-linearity. The next logical step is to do a practical design and refine/benchmark our simulations with, taking into considerations other physical challenges involved.
Presented in Appendices A−J (Figures A1−A10) in the below link to substantiate the tabulated results.
https://drive.google.com/drive/folders/1eH5DNrio6jBVy80Yno2692DxJpTOGYQn?usp=sharing
Thanks to the Cape Peninsula University of Technology (CPUT) and HySA Systems at the University of the Western Cape (UWC), Cape Town, South Africa for funding the study.
The data presented in this study are available on request from the corresponding author. The data are not currently publicly available due to ongoing research work.
The authors declare no conflict of interest. The funders had no role in the design of the study; in the collection, analyses, or interpretation of data; in the writing of the manuscript, or in the decision to publish the results.
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1. | Mamdouh El Haj Assad, Siamak Hoseinzadeh, Editorial to the 'Special Issue-Analyzing energy storage systems for the applications of renewable energy sources' of AIMS Energy, 2022, 10, 2333-8334, 1074, 10.3934/energy.2022050 | |
2. | Viorel Ionescu, Performance analysis of thermoelectric power-generation system with natural convection cooling, 2023, 9, 23524847, 123, 10.1016/j.egyr.2022.12.105 | |
3. | Viorel Ionescu, Anisoara Arleziana Neagu, 2022, Performance Analysis of Thermoelectric Cooler — Thermoelectric Generator System for Heat Recovery Applications, 978-1-6654-6101-6, 31, 10.1109/SIITME56728.2022.9987959 | |
4. | Rafael Zárate-Miñano, Pablo Fernández-Yáñez, Javier de las Morenas, Octavio Armas, A novel mathematical optimization method to obtain the maximum-power electrical configuration of thermoelectric generators for energy harvesting, 2024, 51, 24519049, 102613, 10.1016/j.tsep.2024.102613 | |
5. | Oscar J. Allen, Jian Kang, Shangshu Qian, Jack J. Hinsch, Lei Zhang, Yun Wang, A theoretical review of passivation technologies in perovskite solar cells, 2024, 4, 2770-5900, 10.20517/energymater.2023.111 | |
6. | Hiba Ali Hussein, Zhonglai Wang, W.K. Alani, J. Zheng, Hao Zheng, M.A. Fayad, Strategy for enhancing energy conversion efficiency and cyclist helmet safety: A theoretical and experimental study of diverse thermoelectric generator models, 2024, 55, 24519049, 102998, 10.1016/j.tsep.2024.102998 | |
7. | Viorel Ionescu, Anişoara Arleziana Neagu, 2023, Investigation of the Energy Conversion Efficiency for a Thermoelectric Generator System with Forced Convection Cooling, 979-8-3503-1063-4, 1, 10.1109/EMES58375.2023.10171737 |
S (µV/K) | r (mΩ) | n | R (Ω) | Z (K-1) | ZT | Th (℃) | Tc (℃) | Vout (V) | Iout (A) | Pout (W) |
375 | 12 | 127 | 1.524 | 0.00191 | 0.7125 | 200 | 50 | 3.558 | 2.353 | 8.371 |
C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | |
TEG_S | 100 | 50 | 25 | 20 | 10 | 10 | 5 | 4 | 2 | 1 |
TEG_P | 1 | 2 | 4 | 5 | 10 | 10 | 20 | 25 | 50 | 100 |
Rt = RL (Ω) | 152.4 | 38.1 | 9.525 | 6.096 | 1.524 | 1.524 | 0.381 | 0.24384 | 0.06096 | 0.01524 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/ Time |
VTEG_Ci/ Time |
ITEG_Ci/ Time |
PTEG_Co/Time | VTEG_Co /Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||
C1 | 100 | 1 | 152.4 | Peak | 941.8/0.65 | 243.4/0.246 | 226.6/1 | 704.6/1.031 | 327.7/1.031 | 2.15/1.031 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 74.814 | ||||||||
MPP | 908.5/0.175 | 203.5/0.175 | 4.465/0.175 | 386.2/0.246 | 242.6/0.246 | 1.592/0.246 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 42.509 | ||||||||||||
Actual | 458.3/0.1 | 116.9/0.1 | 3.92/0.1 | 88.45/0.1 | 116.1/0.1 | 0.7618/0.1 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 19.299 | ||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||
C1 | 100 | 1 | 152.4 | Peak | 2342/0.1 | 597.5/0.1 | 226.6/1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 226.6/0.1 | 33.127 | |||||||||||
MPP | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 4.28/0.114 | 31.956 | |||||||||||||||
Actual | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2801/0.1 | 714.4/0.1 | 3.92/0.1 | 16.362 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci /Time | VTEG_Ci /Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co /Time | ITEG_Co /Time | Ts /Time | Tp/Time | Tt /Time | Rt (Ω)/Time | |||||||
C2 | 50 | 2 | 38.1 | Peak|*MPP | 915.3/0.23 | 173.7/0.261 | 5.609/0.174 | *784.7/0.261 | 172.9/0.261 | 4.538/0.261 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 85.731 | |||||
Actual | 822.3/0.2 | 154.8/0.2 | 5.312/0.2 | 622.6/0.2 | 154/0.2 | 4.042/0.2 | 50/0.2 | 2/0.2 | 100/0.2 | 38.1/0.2 | 75.714 | |||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||
C2 | 50 | 2 | 38.1 | Peak | 2581/0.109 | 624.8/0.1 | 5.609/0.174 | 152.4/0.1 | 3043/0.123 | 714.4/0.1 | 5.609/0.174 | 30.079 | ||||||||
Actual | 1075/0.2 | 202.4/0.2 | 5.312/0.2 | 38.1/0.2 | 1897/0.2 | 357.2/0.2 | 5.312/0.2 | 43.347 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C3 | 25 | 4 | 9.525 | Peak|*MPP | 882.3/0.279 | 91.16/0.292 | 9.833/0.268 | *857.5/0.292 | 90.37/0.292 | 9.488/0.292 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.189 | |||||||||||
Actual | 836.9/0.3 | 90.84/0.3 | 9.213/0.3 | 828.4/0.3 | 88.83/0.3 | 9.326/0.3 | 25/0.3 | 4/0.3 | 100/0.3 | 9.525/0.3 | 98.996 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_Int /Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C3 | 25 | 4 | 9.525 | Peak | 3154/0.129 | 673.5/0.1 | 9.833/0.268 | 152.4/0.1 | 3427/0.138 | 714.4/0.1 | 9.833/0.268 | 25.745 | ||||||||||||||
Actual | 808.5/0.3 | 87.76/0.3 | 9.213/0.3 | 9.525/0.3 | 1645/0.3 | 178.6/0.3 | 9.213/0.3 | 50.875 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C4 | 20 | 5 | 6.096 | Peak|*MPP | 887.4/0.423 | 73.68/0.431 | 12.1/0.419 | *871.6/0.431 | 72.89/0.431 | 11.96/0.431 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 98.219 | |||||||||||
Actual | 837.1/0.4 | 71.94/0.4 | 11.64/0.4 | 830.3/0.4 | 71.14/0.4 | 11.67/0.4 | 20/0.4 | 5/0.4 | 100/0.4 | 6.096/0.4 | 99.187 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_Int /Time | RTEG_Int /Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C4 | 20 | 5 | 6.096 | Peak | 3321/0.134 | 686.5/0.1 | 12.1/0.419 | 152.4/0.1 | 3525/0.141 | 714.4/0.1 | 12.1/0.419 | 25.174 | ||||||||||||||
Actual | 825.4/0.4 | 70.93/0.4 | 11.64/0.4 | 6.096/0.4 | 1662/0.4 | 142.9/0.4 | 11.64/0.4 | 50.367 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||||||
C5 | 10 | 10 | 1.524 | Peak|*MPP | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | *870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/ 0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | ||||||||||||
Actual | 836.9/0.5 | 36.29/0.5 | 23.06/0.5 | 828.1/0.5 | 35.53/0.5 | 23.31/0.5 | 10/0.5 | 10/0.5 | 100/0.5 | 1.524/0.5 | 98.948 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t /Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C5 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 | |||||||||||||||
Actual | 810.5/0.5 | 35.15/0.5 | 23.06/0.5 | 1.524/0.5 | 1647/0.5 | 71.44/0.5 | 23.06/0.5 | 50.814 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci /Time | VTEG_Ci /Time | ITEG_Ci /Time | PTEG_Co /Time | VTEG_Co /Time | ITEG_Co /Time | Ts /Time | Tp /Time | Tt /Time | Rt (Ω)/Time | ||||||||||||||
C6 | 10 | 10 | 1.524 | Peak | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | 870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | ||||||||||||
MPP | 884/0.623 | 37.09/0.625 | 23.84/0.621 | 864.5/0.625 | 36.3/0.625 | 23.82/0.625 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.794 | ||||||||||||||||
Actual | 837.1/0.6 | 36.12/0.6 | 23.18/0.6 | 818.5/0.6 | 35.3 /0.6 | 23.17/0.6 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.778 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C6 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 | |||||||||||||||
Actual | 818.5/0.6 | 35.32/0.6 | 23.18/0.6 | 1.524/0.6 | 1656/0.6 | 71.44/0.6 | 23.18/0.6 | 50.549 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω) /Time | ||||||||||||
C7 | 5 | 20 | 0.381 | *MPP | *893.6/0.674 | 18.85/0.674 | 47.39/0.674 | *855.6/0.675 | 18.06/0.675 | 47.39/0.675 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 95.747 | ||||||||||
Actual | 836.7/0.7 | 18.25/0.7 | 45.84/0.7 | 805.3/0.7 | 17.52/0.7 | 45.97/0.7 | 5/0.7 | 20/0.7 | 100/0.7 | 0.381/0.7 | 96.247 | ||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||
C7 | 5 | 20 | 0.381 | Peak | 3719/0.148 | 711.8/0.1 | 47.39/0.674 | 152.4/0.1 | 3743/0.149 | 714.4/0.1 | 47.39/0.674 | 23.874 | |||||||||||||
Actual | 800.6/0.7 | 17.46/0.7 | 45.84/0.7 | 0.381/0.7 | 1637/0.7 | 35.72/0.7 | 45.84/0.7 | 51.112 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C8 | 4 | 25 | 0.24384 | *MPP | *878.6/0.822 | 15.04/0.822 | 58.41/0.823 | *831.8/0.824 | 14.24/0.824 | 58.40/0.824 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 94.673 | |||||||||||
Actual | 836.5/0.8 | 14.68/0.8 | 56.96/0.8 | 791.6/0.8 | 13.89/0.8 | 56.98/0.8 | 4/0.8 | 25/0.8 | 100/0.8 | 0.2438/0.8 | 94.632 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C8 | 4 | 25 | 0.24384 | Peak | 3732/0.149 | 712.4/0.1 | 58.41/0.823 | 152.4/0.1 | 3750/0.149 | 714.4/0.1 | 58.41/0.823 | 23.429 | ||||||||||||||
Actual | 791.3/0.8 | 13.89/0.8 | 56.96/0.8 | 0.2438/0.8 | 1628/0.8 | 28.57/0.8 | 56.96/0.8 | 51.382 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/ Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||||||
C9 | 2 | 50 | 0.06096 | Peak|*MPP | 902.8/0.871 | 7.845/0.867 | 115.2/0.875 | *809.4/0.875 | 7.024/0.875 | 115.2/0.875 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 89.654 | ||||||||||||
Actual | 835.3/0.9 | 7.475/0.9 | 111.8/0.9 | 762.1/0.9 | 6.816/0.9 | 111.8/0.9 | 2.00/0.9 | 50/0.9 | 100/0.9 | 0.06096/0.9 | 91.237 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C9 | 2 | 50 | 0.06096 | Peak | 3750/0.15 | 713.3/0.1 | 115.2/0.875 | 152.4/0.1 | 3758/0.15 | 714.4/0.1 | 115.2/0.875 | 24.023 | |||||||||||||||
Actual | 761.4/0.9 | 6.813/0.9 | 111.8/0.9 | 0.06096/0.9 | 1597/0.9 | 14.29/0.9 | 111.8/0.9 | 52.304 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C10 | 1 | 100 | 0.01524 | Peak|*MPP | 918.4/0.965 | 4.268/0. 949 | 218.8/0.979 | *729.5/0.979 | 3.334/0.979 | 218.8/0.979 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 79.432 | |||||||||||
Actual | 831.2/1 | 3.872/1 | 214.7/1 | 702.4/1 | 3.272/1 | 214.7/1 | 1.00/1 | 100/1 | 100/1 | 0.01524/1 | 84.504 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int /Time | RTEG_Int /Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C10 | 1 | 100 | 0.01524 | Peak | 3754/0.15 | 713.5/0.1 | 218.8/0.979 | 152.4/0.1 | 3761/0.15 | 714.4/0.1 | 218.8/0.979 | 24.419 | ||||||||||||||
Actual | 702.3/1 | 3.272/1 | 214.7/1 | 0.01524/1 | 1533/1 | 7.144/1 | 214.7/1 | 54.220 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||
C1 | 100 | 1 | 152.4 | Peak | 941.8/0.65 | 243.4/0.246 | 226.6/1 | 704.6/1.031 | 327.7/1.031 | 2.15/1.031 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 74.814 | |
MPP | 908.5/0.175 | 203.5/0.175 | 4.465/0.175 | 386.2/0.246 | 242.6/0.246 | 1.592/0.246 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 42.509 | |||||
Actual | 458.3/0.1 | 116.9/0.1 | 3.92/0.1 | 88.45/0.1 | 116.1/0.1 | 0.7618/0.1 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 19.299 | |||||
C2 | 50 | 2 | 38.1 | Peak|*MPP | 915.3/0.23 | 173.7/0.261 | 5.609/0.174 | *784.7/0.261 | 172.9/0.261 | 4.538/0.261 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 85.731 | |
Actual | 822.3/0.2 | 154.8/0.2 | 5.312/0.2 | 622.6/0.2 | 154/0.2 | 4.042/0.2 | 50/0.2 | 2/0.2 | 100/0.2 | 38.1/0.2 | 75.714 | |||||
C3 | 25 | 4 | 9.525 | Peak|*MPP | 882.3/0.279 | 91.16/0.292 | 9.833/0.268 | *857.5/0.292 | 90.37/0.292 | 9.488/0.292 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.189 | |
Actual | 836.9/0.3 | 90.84/0.3 | 9.213/0.3 | 828.4/0.3 | 88.83/0.3 | 9.326/0.3 | 25/0.3 | 4/0.3 | 100/0.3 | 9.525/0.3 | 98.996 | |||||
C4 | 20 | 5 | 6.096 | Peak |*MPP | 887.4/0.423 | 73.68/0.431 | 12.1/0.419 | *871.6/0.431 | 72.89/0.431 | 11.96/0.431 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 98.219 | |
Actual | 837.1/0.4 | 71.94/0.4 | 11.64/0.4 | 830.3/0.4 | 71.14/0.4 | 11.67/0.4 | 20/0.4 | 5/0.4 | 100/0.4 | 6.096/0.4 | 99.187 | |||||
C5 | 10 | 10 | 1.524 | Peak |*MPP | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | *870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | |
Actual | 836.9/0.5 | 36.29/0.5 | 23.06/0.5 | 828.1/0.5 | 35.53/0.5 | 23.31/0.5 | 10/0.5 | 10/0.5 | 100/0.5 | 1.524/0.5 | 98.948 | |||||
C6 | 10 | 10 | 1.524 | Peak | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | 870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | |
MPP | 884/0.623 | 37.09/0.625 | 23.84/0.621 | 864.5/0.625 | 36.3/0.625 | 23.82/0.625 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.794 | |||||
Actual | 837.1/0.6 | 36.12/0.6 | 23.18/0.6 | 818.5/0.6 | 35.32/0.6 | 23.17/0.6 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.778 | |||||
C7 | 5 | 20 | 0.381 | *MPP | *893.6/0.674 | 18.85/0.674 | 47.39/0.674 | *855.6/0.675 | 18.06/0.675 | 47.39/0.675 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 95.747 | |
Actual | 836.7/0.7 | 18.25/0.7 | 45.84/0.7 | 805.3/0.7 | 17.52/0.7 | 45.97/0.7 | 5/0.7 | 20/0.7 | 100/0.7 | 0.381/0.7 | 96.247 | |||||
C8 | 4 | 25 | 0.24384 | *MPP | *878.6/0.822 | 15.04/0.822 | 58.41/0.823 | *831.8/0.824 | 14.24/0.824 | 58.40/0.824 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 94.673 | |
Actual | 836.5/0.8 | 14.68/0.8 | 56.96/0.8 | 791.6/0.8 | 13.89/0.8 | 56.98/0.8 | 4/0.8 | 25/0.8 | 100/0.8 | 0.2438/0.8 | 94.632 | |||||
C9 | 2 | 50 | 0.06096 | Peak|*MPP | 902.8/0.871 | 7.845/0.867 | 115.2/0.875 | *809.4/0.875 | 7.024/0.875 | 115.2/0.875 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 89.654 | |
Actual | 835.3/0.9 | 7.475/0.9 | 111.8/0.9 | 762.1/0.9 | 6.816/0.9 | 111.8/0.9 | 2.00/0.9 | 50/0.9 | 100/0.9 | 0.06096/0.9 | 91.237 | |||||
C10 | 1 | 100 | 0.01524 | Peak|*MPP | 918.4/0.965 | 4.268/0. 949 | 218.8/0.979 | *729.5/0.979 | 3.334/0.979 | 218.8/0.979 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 79.432 | |
Actual | 831.2/1 | 3.872/1 | 214.7/1 | 702.4/1 | 3.272/1 | 214.7/1 | 1.00/1 | 100/1 | 100/1 | 0.01524/1 | 84.504 |
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||
C1 | 100 | 1 | 152.4 | Peak | 2342/0.1 | 597.5/0.1 | 226.6/1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 226.6/0.1 | 33.127 |
MPP | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 4.28/0.114 | 31.956 | ||||
Actual | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2801/0.1 | 714.4/0.1 | 3.92/0.1 | 16.362 | ||||
C2 | 50 | 2 | 38.1 | Peak | 2581/0.109 | 624.8/0.1 | 5.609/0.174 | 152.4/0.1 | 3043/0.123 | 714.4/0.1 | 5.609/0.174 | 30.079 |
Actual | 1075/0.2 | 202.4/0.2 | 5.312/0.2 | 38.1/0.2 | 1897/0.2 | 357.2/0.2 | 5.312/0.2 | 43.347 | ||||
C3 | 25 | 4 | 9.525 | Peak | 3154/0.129 | 673.5/0.1 | 9.833/0.268 | 152.4/0.1 | 3427/0.138 | 714.4/0.1 | 9.833/0.268 | 25.745 |
Actual | 808.5/0.3 | 87.76/0.3 | 9.213/0.3 | 9.525/0.3 | 1645/0.3 | 178.6/0.3 | 9.213/0.3 | 50.875 | ||||
C4 | 20 | 5 | 6.096 | Peak | 3321/0.134 | 686.5/0.1 | 12.1/0.419 | 152.4/0.1 | 3525/0.141 | 714. 4/0.1 | 12.1/0.419 | 25.174 |
Actual | 825.4/0.4 | 70.93/0.4 | 11.64/0.4 | 6.096/0.4 | 1662/0.4 | 142.9/0.4 | 11.64/0.4 | 50.367 | ||||
C5 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 |
Actual | 810.5/0.5 | 35.15/0.5 | 23.06/0.5 | 1.524/0.5 | 1647/0.5 | 71.44/0.5 | 23.06/0.5 | 50.814 | ||||
C6 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 |
Actual | 818.5/0.6 | 35.32/0.6 | 23.18/0.6 | 1.524/0.6 | 1656/0.6 | 71.44/0.6 | 23.18/0.6 | 50.549 | ||||
C7 | 5 | 20 | 0.381 | Peak | 3719/0.148 | 711.8/0.1 | 47.39/0.674 | 152.4/0.1 | 3743/0.149 | 714.4/0.1 | 47.39/0.674 | 23.874 |
Actual | 800.6/0.7 | 17.46/0.7 | 45.84/0.7 | 0.381/0.7 | 1637/0.7 | 35.72/0.7 | 45.84/0.7 | 51.112 | ||||
C8 | 4 | 25 | 0.24384 | Peak | 3732/0.149 | 712.4/0.1 | 58.41/0.823 | 152.4/0.1 | 3750/0.149 | 714.4/0.1 | 58.41/0.823 | 23.429 |
Actual | 791.3 0.8 | 13.89/0.8 | 56.96/0.8 | 0.2438/0.8 | 1628/0.8 | 28.57/0.8 | 56.96/0.8 | 51.382 | ||||
C9 | 2 | 50 | 0.06096 | Peak | 3750/0.15 | 713.3/0.1 | 115.2/0.875 | 152.4/0.1 | 3758/0.15 | 714.4/0.1 | 115.2/0.875 | 24.023 |
Actual | 761.4/0.9 | 6.813/0.9 | 111.8/0.9 | 0.06096/0.9 | 1597/0.9 | 14.29/0.9 | 111.8/0.9 | 52.304 | ||||
C10 | 1 | 100 | 0.01524 | Peak | 3754/0.15 | 713.5/0.1 | 218.8/0.979 | 152.4/0.1 | 3761/0.15 | 714.4/0.1 | 218.8/0.979 | 24.419 |
Actual | 702.3/1.0 | 3.272/1.0 | 214.7/1.0 | 0.01524/1.0 | 1533/1.0 | 7.144/1.0 | 214.7/1.0 | 54.220 | ||||
*Note: where applicable in the tables, *MPP means MPP is also Peak. |
S (µV/K) | r (mΩ) | n | R (Ω) | Z (K-1) | ZT | Th (℃) | Tc (℃) | Vout (V) | Iout (A) | Pout (W) |
375 | 12 | 127 | 1.524 | 0.00191 | 0.7125 | 200 | 50 | 3.558 | 2.353 | 8.371 |
C1 | C2 | C3 | C4 | C5 | C6 | C7 | C8 | C9 | C10 | |
TEG_S | 100 | 50 | 25 | 20 | 10 | 10 | 5 | 4 | 2 | 1 |
TEG_P | 1 | 2 | 4 | 5 | 10 | 10 | 20 | 25 | 50 | 100 |
Rt = RL (Ω) | 152.4 | 38.1 | 9.525 | 6.096 | 1.524 | 1.524 | 0.381 | 0.24384 | 0.06096 | 0.01524 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/ Time |
VTEG_Ci/ Time |
ITEG_Ci/ Time |
PTEG_Co/Time | VTEG_Co /Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||
C1 | 100 | 1 | 152.4 | Peak | 941.8/0.65 | 243.4/0.246 | 226.6/1 | 704.6/1.031 | 327.7/1.031 | 2.15/1.031 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 74.814 | ||||||||
MPP | 908.5/0.175 | 203.5/0.175 | 4.465/0.175 | 386.2/0.246 | 242.6/0.246 | 1.592/0.246 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 42.509 | ||||||||||||
Actual | 458.3/0.1 | 116.9/0.1 | 3.92/0.1 | 88.45/0.1 | 116.1/0.1 | 0.7618/0.1 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 19.299 | ||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||
C1 | 100 | 1 | 152.4 | Peak | 2342/0.1 | 597.5/0.1 | 226.6/1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 226.6/0.1 | 33.127 | |||||||||||
MPP | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 4.28/0.114 | 31.956 | |||||||||||||||
Actual | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2801/0.1 | 714.4/0.1 | 3.92/0.1 | 16.362 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci /Time | VTEG_Ci /Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co /Time | ITEG_Co /Time | Ts /Time | Tp/Time | Tt /Time | Rt (Ω)/Time | |||||||
C2 | 50 | 2 | 38.1 | Peak|*MPP | 915.3/0.23 | 173.7/0.261 | 5.609/0.174 | *784.7/0.261 | 172.9/0.261 | 4.538/0.261 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 85.731 | |||||
Actual | 822.3/0.2 | 154.8/0.2 | 5.312/0.2 | 622.6/0.2 | 154/0.2 | 4.042/0.2 | 50/0.2 | 2/0.2 | 100/0.2 | 38.1/0.2 | 75.714 | |||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||
C2 | 50 | 2 | 38.1 | Peak | 2581/0.109 | 624.8/0.1 | 5.609/0.174 | 152.4/0.1 | 3043/0.123 | 714.4/0.1 | 5.609/0.174 | 30.079 | ||||||||
Actual | 1075/0.2 | 202.4/0.2 | 5.312/0.2 | 38.1/0.2 | 1897/0.2 | 357.2/0.2 | 5.312/0.2 | 43.347 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C3 | 25 | 4 | 9.525 | Peak|*MPP | 882.3/0.279 | 91.16/0.292 | 9.833/0.268 | *857.5/0.292 | 90.37/0.292 | 9.488/0.292 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.189 | |||||||||||
Actual | 836.9/0.3 | 90.84/0.3 | 9.213/0.3 | 828.4/0.3 | 88.83/0.3 | 9.326/0.3 | 25/0.3 | 4/0.3 | 100/0.3 | 9.525/0.3 | 98.996 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_Int /Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C3 | 25 | 4 | 9.525 | Peak | 3154/0.129 | 673.5/0.1 | 9.833/0.268 | 152.4/0.1 | 3427/0.138 | 714.4/0.1 | 9.833/0.268 | 25.745 | ||||||||||||||
Actual | 808.5/0.3 | 87.76/0.3 | 9.213/0.3 | 9.525/0.3 | 1645/0.3 | 178.6/0.3 | 9.213/0.3 | 50.875 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C4 | 20 | 5 | 6.096 | Peak|*MPP | 887.4/0.423 | 73.68/0.431 | 12.1/0.419 | *871.6/0.431 | 72.89/0.431 | 11.96/0.431 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 98.219 | |||||||||||
Actual | 837.1/0.4 | 71.94/0.4 | 11.64/0.4 | 830.3/0.4 | 71.14/0.4 | 11.67/0.4 | 20/0.4 | 5/0.4 | 100/0.4 | 6.096/0.4 | 99.187 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_Int /Time | RTEG_Int /Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C4 | 20 | 5 | 6.096 | Peak | 3321/0.134 | 686.5/0.1 | 12.1/0.419 | 152.4/0.1 | 3525/0.141 | 714.4/0.1 | 12.1/0.419 | 25.174 | ||||||||||||||
Actual | 825.4/0.4 | 70.93/0.4 | 11.64/0.4 | 6.096/0.4 | 1662/0.4 | 142.9/0.4 | 11.64/0.4 | 50.367 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||||||
C5 | 10 | 10 | 1.524 | Peak|*MPP | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | *870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/ 0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | ||||||||||||
Actual | 836.9/0.5 | 36.29/0.5 | 23.06/0.5 | 828.1/0.5 | 35.53/0.5 | 23.31/0.5 | 10/0.5 | 10/0.5 | 100/0.5 | 1.524/0.5 | 98.948 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_In t /Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C5 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 | |||||||||||||||
Actual | 810.5/0.5 | 35.15/0.5 | 23.06/0.5 | 1.524/0.5 | 1647/0.5 | 71.44/0.5 | 23.06/0.5 | 50.814 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci /Time | VTEG_Ci /Time | ITEG_Ci /Time | PTEG_Co /Time | VTEG_Co /Time | ITEG_Co /Time | Ts /Time | Tp /Time | Tt /Time | Rt (Ω)/Time | ||||||||||||||
C6 | 10 | 10 | 1.524 | Peak | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | 870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | ||||||||||||
MPP | 884/0.623 | 37.09/0.625 | 23.84/0.621 | 864.5/0.625 | 36.3/0.625 | 23.82/0.625 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.794 | ||||||||||||||||
Actual | 837.1/0.6 | 36.12/0.6 | 23.18/0.6 | 818.5/0.6 | 35.3 /0.6 | 23.17/0.6 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.778 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int /Time | ITEG_In t/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C6 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 | |||||||||||||||
Actual | 818.5/0.6 | 35.32/0.6 | 23.18/0.6 | 1.524/0.6 | 1656/0.6 | 71.44/0.6 | 23.18/0.6 | 50.549 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω) /Time | ||||||||||||
C7 | 5 | 20 | 0.381 | *MPP | *893.6/0.674 | 18.85/0.674 | 47.39/0.674 | *855.6/0.675 | 18.06/0.675 | 47.39/0.675 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 95.747 | ||||||||||
Actual | 836.7/0.7 | 18.25/0.7 | 45.84/0.7 | 805.3/0.7 | 17.52/0.7 | 45.97/0.7 | 5/0.7 | 20/0.7 | 100/0.7 | 0.381/0.7 | 96.247 | ||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
|||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||
C7 | 5 | 20 | 0.381 | Peak | 3719/0.148 | 711.8/0.1 | 47.39/0.674 | 152.4/0.1 | 3743/0.149 | 714.4/0.1 | 47.39/0.674 | 23.874 | |||||||||||||
Actual | 800.6/0.7 | 17.46/0.7 | 45.84/0.7 | 0.381/0.7 | 1637/0.7 | 35.72/0.7 | 45.84/0.7 | 51.112 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C8 | 4 | 25 | 0.24384 | *MPP | *878.6/0.822 | 15.04/0.822 | 58.41/0.823 | *831.8/0.824 | 14.24/0.824 | 58.40/0.824 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 94.673 | |||||||||||
Actual | 836.5/0.8 | 14.68/0.8 | 56.96/0.8 | 791.6/0.8 | 13.89/0.8 | 56.98/0.8 | 4/0.8 | 25/0.8 | 100/0.8 | 0.2438/0.8 | 94.632 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
||||||||||||||||||||||
C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C8 | 4 | 25 | 0.24384 | Peak | 3732/0.149 | 712.4/0.1 | 58.41/0.823 | 152.4/0.1 | 3750/0.149 | 714.4/0.1 | 58.41/0.823 | 23.429 | ||||||||||||||
Actual | 791.3/0.8 | 13.89/0.8 | 56.96/0.8 | 0.2438/0.8 | 1628/0.8 | 28.57/0.8 | 56.96/0.8 | 51.382 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/ Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | ||||||||||||||
C9 | 2 | 50 | 0.06096 | Peak|*MPP | 902.8/0.871 | 7.845/0.867 | 115.2/0.875 | *809.4/0.875 | 7.024/0.875 | 115.2/0.875 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 89.654 | ||||||||||||
Actual | 835.3/0.9 | 7.475/0.9 | 111.8/0.9 | 762.1/0.9 | 6.816/0.9 | 111.8/0.9 | 2.00/0.9 | 50/0.9 | 100/0.9 | 0.06096/0.9 | 91.237 | ||||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | |||||||||||||||||
C9 | 2 | 50 | 0.06096 | Peak | 3750/0.15 | 713.3/0.1 | 115.2/0.875 | 152.4/0.1 | 3758/0.15 | 714.4/0.1 | 115.2/0.875 | 24.023 | |||||||||||||||
Actual | 761.4/0.9 | 6.813/0.9 | 111.8/0.9 | 0.06096/0.9 | 1597/0.9 | 14.29/0.9 | 111.8/0.9 | 52.304 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||||||||||||
C10 | 1 | 100 | 0.01524 | Peak|*MPP | 918.4/0.965 | 4.268/0. 949 | 218.8/0.979 | *729.5/0.979 | 3.334/0.979 | 218.8/0.979 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 79.432 | |||||||||||
Actual | 831.2/1 | 3.872/1 | 214.7/1 | 702.4/1 | 3.272/1 | 214.7/1 | 1.00/1 | 100/1 | 100/1 | 0.01524/1 | 84.504 | |||||||||||||||
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int /Time | RTEG_Int /Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||||||||||||||||
C10 | 1 | 100 | 0.01524 | Peak | 3754/0.15 | 713.5/0.1 | 218.8/0.979 | 152.4/0.1 | 3761/0.15 | 714.4/0.1 | 218.8/0.979 | 24.419 | ||||||||||||||
Actual | 702.3/1 | 3.272/1 | 214.7/1 | 0.01524/1 | 1533/1 | 7.144/1 | 214.7/1 | 54.220 |
Simulation Parameters Settings | Simulated Measurements |
TEGs Conv_Pin (W), Vin (V) & Iin (A) | TEGs Conv_Po (W), Vo (V) & Io (A) | TEGs series, parallel, total & int resistance | TEGs Conv Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Ci/Time | VTEG_Ci/Time | ITEG_Ci/Time | PTEG_Co/Time | VTEG_Co/Time | ITEG_Co/Time | Ts/Time | Tp/Time | Tt/Time | Rt (Ω)/Time | |||
C1 | 100 | 1 | 152.4 | Peak | 941.8/0.65 | 243.4/0.246 | 226.6/1 | 704.6/1.031 | 327.7/1.031 | 2.15/1.031 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 74.814 | |
MPP | 908.5/0.175 | 203.5/0.175 | 4.465/0.175 | 386.2/0.246 | 242.6/0.246 | 1.592/0.246 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 42.509 | |||||
Actual | 458.3/0.1 | 116.9/0.1 | 3.92/0.1 | 88.45/0.1 | 116.1/0.1 | 0.7618/0.1 | 100/0.1 | 1/0.1 | 100/0.1 | 152.4/0.1 | 19.299 | |||||
C2 | 50 | 2 | 38.1 | Peak|*MPP | 915.3/0.23 | 173.7/0.261 | 5.609/0.174 | *784.7/0.261 | 172.9/0.261 | 4.538/0.261 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 85.731 | |
Actual | 822.3/0.2 | 154.8/0.2 | 5.312/0.2 | 622.6/0.2 | 154/0.2 | 4.042/0.2 | 50/0.2 | 2/0.2 | 100/0.2 | 38.1/0.2 | 75.714 | |||||
C3 | 25 | 4 | 9.525 | Peak|*MPP | 882.3/0.279 | 91.16/0.292 | 9.833/0.268 | *857.5/0.292 | 90.37/0.292 | 9.488/0.292 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.189 | |
Actual | 836.9/0.3 | 90.84/0.3 | 9.213/0.3 | 828.4/0.3 | 88.83/0.3 | 9.326/0.3 | 25/0.3 | 4/0.3 | 100/0.3 | 9.525/0.3 | 98.996 | |||||
C4 | 20 | 5 | 6.096 | Peak |*MPP | 887.4/0.423 | 73.68/0.431 | 12.1/0.419 | *871.6/0.431 | 72.89/0.431 | 11.96/0.431 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 98.219 | |
Actual | 837.1/0.4 | 71.94/0.4 | 11.64/0.4 | 830.3/0.4 | 71.14/0.4 | 11.67/0.4 | 20/0.4 | 5/0.4 | 100/0.4 | 6.096/0.4 | 99.187 | |||||
C5 | 10 | 10 | 1.524 | Peak |*MPP | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | *870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | |
Actual | 836.9/0.5 | 36.29/0.5 | 23.06/0.5 | 828.1/0.5 | 35.53/0.5 | 23.31/0.5 | 10/0.5 | 10/0.5 | 100/0.5 | 1.524/0.5 | 98.948 | |||||
C6 | 10 | 10 | 1.524 | Peak | 890.3/0.475 | 37.22/0.477 | 23.93/0.473 | 870.7/0.478 | 36.43/0.478 | 23.9/0.478 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 97.798 | |
MPP | 884/0.623 | 37.09/0.625 | 23.84/0.621 | 864.5/0.625 | 36.3/0.625 | 23.82/0.625 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.794 | |||||
Actual | 837.1/0.6 | 36.12/0.6 | 23.18/0.6 | 818.5/0.6 | 35.32/0.6 | 23.17/0.6 | 10/0.6 | 10/0.6 | 100/0.6 | 1.524/0.6 | 97.778 | |||||
C7 | 5 | 20 | 0.381 | *MPP | *893.6/0.674 | 18.85/0.674 | 47.39/0.674 | *855.6/0.675 | 18.06/0.675 | 47.39/0.675 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 95.747 | |
Actual | 836.7/0.7 | 18.25/0.7 | 45.84/0.7 | 805.3/0.7 | 17.52/0.7 | 45.97/0.7 | 5/0.7 | 20/0.7 | 100/0.7 | 0.381/0.7 | 96.247 | |||||
C8 | 4 | 25 | 0.24384 | *MPP | *878.6/0.822 | 15.04/0.822 | 58.41/0.823 | *831.8/0.824 | 14.24/0.824 | 58.40/0.824 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 94.673 | |
Actual | 836.5/0.8 | 14.68/0.8 | 56.96/0.8 | 791.6/0.8 | 13.89/0.8 | 56.98/0.8 | 4/0.8 | 25/0.8 | 100/0.8 | 0.2438/0.8 | 94.632 | |||||
C9 | 2 | 50 | 0.06096 | Peak|*MPP | 902.8/0.871 | 7.845/0.867 | 115.2/0.875 | *809.4/0.875 | 7.024/0.875 | 115.2/0.875 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 89.654 | |
Actual | 835.3/0.9 | 7.475/0.9 | 111.8/0.9 | 762.1/0.9 | 6.816/0.9 | 111.8/0.9 | 2.00/0.9 | 50/0.9 | 100/0.9 | 0.06096/0.9 | 91.237 | |||||
C10 | 1 | 100 | 0.01524 | Peak|*MPP | 918.4/0.965 | 4.268/0. 949 | 218.8/0.979 | *729.5/0.979 | 3.334/0.979 | 218.8/0.979 | 100/0.1 | 100/1 | 112.5/0.15 | 152.4/0.1 | 79.432 | |
Actual | 831.2/1 | 3.872/1 | 214.7/1 | 702.4/1 | 3.272/1 | 214.7/1 | 1.00/1 | 100/1 | 100/1 | 0.01524/1 | 84.504 |
Simulation Parameters Settings | Simulated Measurements |
TEG(s) Internal Power (W), Voltage (V), Current(A) & Resistance (Ω) | TEG(s) Ideal Power (W), Voltage (V) & Current (A) | TEGs Source Eff (%) |
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C | TEG-S | TEG-P | RL(Ω) | PTEG_Int/Time | VTEG_Int/Time | ITEG_Int/Time | RTEG_Int/Time | PTEG_OC/Time | VTEG_OC/Time | ITEG_OC/Time | ||
C1 | 100 | 1 | 152.4 | Peak | 2342/0.1 | 597.5/0.1 | 226.6/1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 226.6/0.1 | 33.127 |
MPP | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2843/0.114 | 714.4/0.1 | 4.28/0.114 | 31.956 | ||||
Actual | 2342/0.1 | 597.5/0.1 | 3.92/0.1 | 152.4/0.1 | 2801/0.1 | 714.4/0.1 | 3.92/0.1 | 16.362 | ||||
C2 | 50 | 2 | 38.1 | Peak | 2581/0.109 | 624.8/0.1 | 5.609/0.174 | 152.4/0.1 | 3043/0.123 | 714.4/0.1 | 5.609/0.174 | 30.079 |
Actual | 1075/0.2 | 202.4/0.2 | 5.312/0.2 | 38.1/0.2 | 1897/0.2 | 357.2/0.2 | 5.312/0.2 | 43.347 | ||||
C3 | 25 | 4 | 9.525 | Peak | 3154/0.129 | 673.5/0.1 | 9.833/0.268 | 152.4/0.1 | 3427/0.138 | 714.4/0.1 | 9.833/0.268 | 25.745 |
Actual | 808.5/0.3 | 87.76/0.3 | 9.213/0.3 | 9.525/0.3 | 1645/0.3 | 178.6/0.3 | 9.213/0.3 | 50.875 | ||||
C4 | 20 | 5 | 6.096 | Peak | 3321/0.134 | 686.5/0.1 | 12.1/0.419 | 152.4/0.1 | 3525/0.141 | 714. 4/0.1 | 12.1/0.419 | 25.174 |
Actual | 825.4/0.4 | 70.93/0.4 | 11.64/0.4 | 6.096/0.4 | 1662/0.4 | 142.9/0.4 | 11.64/0.4 | 50.367 | ||||
C5 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 |
Actual | 810.5/0.5 | 35.15/0.5 | 23.06/0.5 | 1.524/0.5 | 1647/0.5 | 71.44/0.5 | 23.06/0.5 | 50.814 | ||||
C6 | 10 | 10 | 1.524 | Peak | 3619/0.144 | 706.5/0.1 | 23.93/0.473 | 152.4/0.1 | 3691/0.147 | 714.4/0.1 | 23.93/0.473 | 24.121 |
Actual | 818.5/0.6 | 35.32/0.6 | 23.18/0.6 | 1.524/0.6 | 1656/0.6 | 71.44/0.6 | 23.18/0.6 | 50.549 | ||||
C7 | 5 | 20 | 0.381 | Peak | 3719/0.148 | 711.8/0.1 | 47.39/0.674 | 152.4/0.1 | 3743/0.149 | 714.4/0.1 | 47.39/0.674 | 23.874 |
Actual | 800.6/0.7 | 17.46/0.7 | 45.84/0.7 | 0.381/0.7 | 1637/0.7 | 35.72/0.7 | 45.84/0.7 | 51.112 | ||||
C8 | 4 | 25 | 0.24384 | Peak | 3732/0.149 | 712.4/0.1 | 58.41/0.823 | 152.4/0.1 | 3750/0.149 | 714.4/0.1 | 58.41/0.823 | 23.429 |
Actual | 791.3 0.8 | 13.89/0.8 | 56.96/0.8 | 0.2438/0.8 | 1628/0.8 | 28.57/0.8 | 56.96/0.8 | 51.382 | ||||
C9 | 2 | 50 | 0.06096 | Peak | 3750/0.15 | 713.3/0.1 | 115.2/0.875 | 152.4/0.1 | 3758/0.15 | 714.4/0.1 | 115.2/0.875 | 24.023 |
Actual | 761.4/0.9 | 6.813/0.9 | 111.8/0.9 | 0.06096/0.9 | 1597/0.9 | 14.29/0.9 | 111.8/0.9 | 52.304 | ||||
C10 | 1 | 100 | 0.01524 | Peak | 3754/0.15 | 713.5/0.1 | 218.8/0.979 | 152.4/0.1 | 3761/0.15 | 714.4/0.1 | 218.8/0.979 | 24.419 |
Actual | 702.3/1.0 | 3.272/1.0 | 214.7/1.0 | 0.01524/1.0 | 1533/1.0 | 7.144/1.0 | 214.7/1.0 | 54.220 | ||||
*Note: where applicable in the tables, *MPP means MPP is also Peak. |