Figure 1.
Schematic view of junctionless GAA FET with ferroelectric.
Citation: Bashir Sajo Mienda, Mohd Shahir Shamsir. Model-driven in Silico glpC Gene Knockout Predicts Increased Succinate Production from Glycerol in Escherichia Coli[J]. AIMS Bioengineering, 2015, 2(2): 40-48. doi: 10.3934/bioeng.2015.2.40
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The planar-type MOSFETs are no longer available due to Short Channel Effects (SCEs), such as an increase in subthreshold swing, off-current, threshold voltage roll-off and Drain Induced Barrier Lowering (DIBL) as the transistor size decreases [1,2,3]. The FinFET structure, which is a tri-gate structure used to solve this problem, also has limitations in scaling, so a transistor with a new structure has been developed [4,5,6]. In particular, FinFET using ferroelectric was developed to solve the increase in power consumption, which is the most problematic due to the reduction in transistor size, which is indispensable for high-speed operation [7,8]. Also, a Gate-All-Around (GAA) FET is being developed as a next-generation transistor structure to overcome the limitations of FinFETs [9,10]. The GAA FET has a structure that maximizes the ability of the gate to control the channel carrier, and numerous studies are currently being conducted on these devices [11,12]. In particular, the junctionless structure [13,14], which makes the doping concentration of the channel and the source/drain region almost the same, is applied to the GAA FET structure as a structure that can solve the difficulty of manufacturing due to the reduction in transistor size [15,16,17].
In addition, to achieve low power consumption, it is also necessary to reduce the subthreshold swing (SS). To overcome the limit of 60 mV/dec for the SS, ferroelectric materials are used, for which Metal-Ferroelectric-Insulator-Semiconductor (MFIS) structures and Metal-Ferroelectric- Metal-Insulator-Semiconductors (MFMIS) are mainly used [18,19]. Compared to the MFMIS structure, the stability of the ferroelectric material in the MFIS structure is independent of the gate leakage current, but gate leakage is ignored in this paper, so an analytical model of subthreshold swing is presented for the junctionless GAA FET of the MFMIS structure with high on-current. Research has been conducted extensively on junction-based MFIS-structured GAA FETs [20,21], but little has been done on junctionless MFMIS-structured GAA FETs.
Rassekh et al. analyzed SCEs such as the SS and DIBL for a channel length of 100 nm for the MFMIS-structured double-gate junctionless FET with ferroelectric [22]. It was found that the change of SS for the ferroelectric thickness could not be observed in the deep subthreshold region when the channel length was about 100 nm. Pahwa et al. analyzed the threshold voltage roll-off, SS, DIBL, etc. up to 10 nm channel length for undoped channel double gate FETs with MFIS and MFMIS structures, but they only used numerical simulation [23]. Sakib et al. analyzed SCEs for ferroelectric GAA FETs, but only numerically simulated junction-based MFIS and MFMIS structures [24]. Choi et al. and Raut et al. analyzed SCEs for junctionless GAA FET using ferroelectric, but only used TCAD [25,26]. Mehta et al., Gaidhane et al. and Kim et al. analyzed the current-voltage characteristics of the ferroelectric MFIS structure, but analyzed only one-dimensionally for the channel radial direction of the long-channel, so the change of SS occurring in the short channel could not be interpreted [27,28,29]. It is necessary, however, to analyze not only the potential distribution along the radial direction of the channel but also along the channel length direction as the size of the transistor decreases. To this end, it is necessary to solve the two-dimensional Poisson equation in the GAA structure. In addition, in the junctionless GAA structure using ferroelectric, it is necessary to know how the charge in the ferroelectric changes according to the gate voltage to interpret the SS in the junctionless GAA FET with ferroelectric. Therefore, in this paper, we will find the solution of Poisson's equation two-dimensionally for the junctionless GAA FET of cylindrical structure with ferroelectric, and derive the drain current-gate voltage relationship using it. From the current-voltage relationship obtained in this way, we will find SS according to the definition of SS and compare it with the value of the analytical SS model presented. Ferroelectric will use the properties of HZO and will use the MFMIS structure, which has been proven in many experiments [30,31]. In addition, we will use the relationship between ferroelectric voltage, inner voltage and outer voltage by the LK (Landau-Khalatnikov) equation.
Figure 1 is the structure of the ferroelectric junctionless GAA FET used in this paper. As shown in Figure 1, the MFMIS structure was used and device parameters are shown in Table 1. Although not shown in Figure 1, Vgs1 is the voltage induced to the inner gate metal, and Vgs2 is the voltage applied to the outer gate metal.
| Device parameter | Symbol | Value |
| Channel length | Lg | 20~60 nm |
| Channel radius | R | 5~10 nm |
| SiO2 thickness | tox | 1~2 nm |
| Doping concentration | Nd | 1018/cm3 |
| Ferroelectric thickness | tfe | 0~10 nm |
| Remanent polarization | Pr | 15~30 $ {\mathtt{μ}} $C/cm2 |
| Coercive field | Ec | 0.8~1.5 MV/cm |
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To obtain the potential distribution within the channel of a MOSFET with a GAA structure, Li's two-dimensional potential model for the r and z directions was used [32]. In other words, the potential in the channel can be obtained as the sum of the one-dimensional solution ${\phi _1}(r)$ of Poisson's equation and the two-dimensional solution ${\phi _2}(r,z)$ of the homogeneous Laplace equation, as follows.
| $ \phi(r, z) = \phi_{1}(r)+\phi_{2}(r, z) $ |
| $ {\phi _1}(r) = - \frac{{q{N_d}}}{{4{\varepsilon _{si}}}}{r^2} + {V_{gs}} - {\phi _{ms}} + \frac{{q{N_d}R}}{{2{C_{ox}}}} + \frac{{q{N_d}{R^2}}}{{4{\varepsilon _{si}}}} $ | (2.1) |
| $ {\phi _2}(r,z) = \sum\limits_{n = 1}^\infty {\left[ {{C_n}\exp \left( {\frac{{{\alpha _n}z}}{R}} \right) + {D_n}\exp \left( { - \frac{{{\alpha _n}z}}{R}} \right)} \right]{J_0}\left( {\frac{{{\alpha _n}r}}{R}} \right)} $ | (2.2) |
where ${\alpha _n}$ is an eigenvalue that satisfies (2.3). Refer to the Cn and Dn in [32]
| $ R{J_0}({\alpha _n}) - \frac{{{\varepsilon _{si}}}}{{{C_{ox}}}}{\alpha _n}{J_1}({\alpha _n}) = 0 $ | (2.3) |
To find the charge in the ferroelectric, the charge in the channel must first be obtained from the relational expression of (2.4).
| $ {Q_{sc}} = - {C_{ox}}({V_{gs1}} - {\phi _{ms}} - {\phi _s}) $ | (2.4) |
At this time, the surface potential ${\phi _s}$ can be obtained as the following (2.5) by substituting r = R into (2.1) and (2.2).
| $ \varphi_{s}(z) = \varphi_{1}(R)+\varphi_{2}(R, z) $ | (2.5) |
|
$
ϕ1(R)=−qNd4εsiR2+Vgs1−ϕms+qNdR2Cox+qNdR24εsi=Vgs1−ϕms+qNdR2Coxϕ2(R,z)=∞∑n=1[Cnexp(αnzR)+Dnexp(−αnzR)]J0(αnRR)=∞∑n=1[Cnexp(αnzR)+Dnexp(−αnzR)]J0(αn)
$
|
where ${\phi _{ms}}$ is the work function difference between the gate metal and semiconductor. Substituting (2.5) into (2.4), the charge in the channel Qsc can be obtained as shown in (2.6) below.
| $ {Q_{sc}} = {C_{ox}}\left\{ {\frac{{q{N_d}R}}{{2{C_{ox}}}} + \sum\limits_{n = 1}^\infty {\left[ {{C_n}\exp \left( {\frac{{{\alpha _n}z}}{R}} \right) + {D_n}\exp \left( { - \frac{{{\alpha _n}z}}{R}} \right)} \right]{J_0}\left( {{\alpha _n}} \right)} } \right\} $ | (2.6) |
Using (2.6), the ferroelectric charge Q can be obtained from (2.7).
| $ 2\pi R{L_g} \times Q = - \int_0^{{L_g}} {\pi R{Q_{sc}}dz} $ | (2.7) |
Here, the ferroelectric charge can be derived as in (2.8).
|
$ Q=−12Lg∫Lg0Qscdz=−qNdR4−Cox2Lg[∞∑n=1[Cnexp(αnLgR)−Dnexp(−αnLgR)−Cn+Dn](Rαn)J0(αn)] $
|
(2.8) |
Using the ferroelectric charge Q, the ferroelectric voltage Vf can be obtained from the following (2.9) by Landau theory.
| $ {V_f} = 2\alpha {t_f}Q + 4\beta {t_f}{Q^3} + 6\gamma {t_f}{Q^5} $ | (2.9) |
|
$ α=−3√34EcPr(m/F)β=3√38EcP3r(m5/F/C2)γ=0 $
|
where Pr is the remanent polarization of the ferroelectric material and Ec is the coercive field. As shown in Table 1, the values of Pr and Ec were within the range derived from various papers in the case of HZO [33,34,35,36]. Using the ferroelectric voltage Vf derived in this way, the relationship between inner gate voltage Vgs1 and outer gate voltage Vgs2 can be expressed as in (2.10) below.
| $ {V_{gs2}} = {V_{gs1}} + {V_f} $ | (2.10) |
Using (2.1) and (2.2), the relationship between drain current and gate voltage can be derived by the following (2.11).
| $ {I_d} = \frac{{2\pi {N_d}{\mu _n}kT\left\{ {1 - \exp \left( {\frac{{ - q{V_{ds}}}}{{kT}}} \right)} \right\}}}{{\int_0^{{L_g}} {\frac{1}{{\int_0^R {r\exp \left\{ {\frac{{q\phi (r,z)}}{{kT}}} \right\}} dr}}} }} $ | (2.11) |
The relationship between drain current and gate voltage obtained using (2.11) is shown in Figure 2(a). As can be seen in Figure 2(a), it was found to be in good agreement with the ISE-TCAD result at tfe = 0, and in Figure 2(b), it was observed that the SS decreased as the ferroelectric thickness increased. In this paper, we propose an analytical SS model consistent with the two-dimensional SS derived in Figure 2.
To obtain the analytical SS model, the SS can be expressed in the following (2.12) by the definition of SS.
| $ SS = \frac{{\partial {V_{gs2}}}}{{\partial (\log {I_{ds}})}} = \ln (10)\left( {\frac{{kT}}{q}} \right){\left( {\frac{{\partial {\phi _{\min }}}}{{\partial {V_{gs2}}}}} \right)^{ - 1}} = \ln (10)\left( {\frac{{kT}}{q}} \right){\left[ {\frac{{\partial \phi (0,{z_{\min }})}}{{\partial {V_{gs2}}}}} \right]^{ - 1}} $ | (2.12) |
Here, r = 0 is substituted since most carriers move along the central axis of the channel in the junctionless structure, and z = zmin, which has the minimum potential value, is substituted [37]. In (2.12), the parenthesis of the last term is as follows.
|
$ ∂ϕ(0,zmin)∂Vgs2=∂∂Vgs2{∑[Cnexp(αnzmin/R)+Dnexp(−αnzmin/R)]J0(0)+ϕ1(0)}=∂∂Vgs2{∑[Cnexp(αnzmin/R)+Dnexp(−αnzmin/R)]}+∂ϕ1(0)∂Vgs2{∵J0(0)=1}=∂ϕ1(0)∂Vgs1∂Vgs1∂Q∂Q∂Vgs2+∑[exp(αnzmin/R)∂Cn∂Vgs2+Cn∂∂Vgs2{exp(αnzmin/R)}+exp(−αnzmin/R)∂Dn∂Vgs2+Dn∂∂Vgs2{exp(−αnzmin/R)}]=∂Vgs1∂Q∂Q∂Vgs2+∑[exp(αnzmin/R)∂Cn∂Vgs2+Cn∂∂Vgs2{exp(αnzmin/R)}+exp(−αnzmin/R)∂Dn∂Vgs2+Dn∂∂Vgs2{exp(−αnzmin/R)}]{∵∂ϕ1(0)∂Vgs1=1} $
|
(2.13) |
The derivative of each term for Vgs2 in (2.13) can be obtained using the parametric differentiation method indicated in the Appendix. Using the formula in the Appendix, the SS can be obtained analytically.
To obtain the analytical SS model, the value of n = 1 had to be used when calculating the zmin value in the Appendix. To prove its validity, the deviation of SSs calculated for n = 1 and n = 32 (the number of n that satisfies (2.3) when the maximum of $\alpha $ is 100) is shown in Figure 3 according to the ratio of the channel length and radius, Lg/R. As shown in Figure 3, the deviation increased as the ratio of channel length and radius decreased, and the deviation was less than 1% regardless of the ferroelectric thickness for Lg/R > 3. In particular, it was found that it is sufficient to calculate only the case of n = 1 when calculating this analytical SS model as the ferroelectric thickness decreases. In general, it will be sufficient to calculate only the case of n = 1 since Lg/R > 2.
In Figure 4, the results of the analytical SS model in the case of n = 1 presented in this paper, the SS derived from the relationship between drain current and gate voltage in (2.11) and the 3D ISE-TCAD simulation value [32] calculated at tfe = 0 nm were compared. As shown in Figure 4, it can be seen that the SS proposed in this paper is reasonable.
To compare the change of SS according to the ferroelectric thickness with the case of using the analytical SS model of this paper and the SS derived from the slope in the subthreshold region of the drain current and gate voltage curve of (2.11), the SSs are shown with the channel length as a parameter in Figure 5. At this time, to maintain the deviation of less than 1%, it was calculated for the case of Lg/R > 4. As can be seen in Figure 5, the SSs from the analytical SS model of this paper agree very well with the SSs derived from the curve of drain current and gate voltage using a 2D potential distribution. As can be observed in Figure 5, it can be seen that the difference between the two values increases as Lg/R decreases. As mentioned in Figure 2(b), the SS decreased as the ferroelectric thickness increased and the change in SS due to the change in ferroelectric thickness decreased as the channel length increased. In particular, SS < 60 mV/dec was exhibited when the channel length was 40 nm or more under the given conditions.
To compare the change of SS with the change of channel radius, Figure 6 shows the change of SS while changing the channel radius R from 5 nm to 10 nm when the channel length is 30 nm under the given conditions. Based on Figure 6, it can be observed that the results of the 2D calculation and the analytical SS model are in good agreement. Since it is in the range of 3 < Lg/R < 6, even if n = 1 was used, the value could be obtained within the deviation range of less than 1%. As the channel radius R increases, SS increases, and it can be observed that the increasing rate $(\Delta SS/\Delta R)$ increases as R increases. In particular, it was found that the case of R = 5 nm, that is, the case of Lg/R = 6, matches very well. Therefore, the analytical SS model of this paper will be very useful.
As shown in Figure 5, it can be seen that SS > 60 mV/dec if Lg < 30 nm under the given conditions. This is the case of remanent polarization ${P_r} = 17\,\mu C/c{m^2}$ and coercive field Ec = 1.2 MV/cm, as shown in Figure 5. The remanent polarization and coercive field values are important factors that determine the hysteresis characteristics of ferroelectric materials, and it is known that the SS value is proportional to the absolute value |Cfe| of the capacitance of ferroelectric materials [38]. Figure 7 shows the contours of SS for the change of Pr and Ec when the channel length is 30 nm while keeping the device parameters the same as in Figure 5. The red dot in Figure 7 shows the SS value calculated under the conditions of Figure 5. As can be seen in Figure 7, the SS decreases as the remanent polarization decreases and the coercive field increases, and it can be observed that a region of SS < 60 mV/dec appears in the range of $15 \leqslant {P_r} \leqslant 16.8\,\mu C/c{m^2}$ and $1.34 \leqslant {E_c} \leqslant 1.5\,MV/cm$. It can be seen that there is a relationship of |Cfe| $ \propto {P_r}/{E_c}$. Therefore, if Pr and Ec satisfying the condition of SS < 60 mV/dec are used, SS < 60 mV/dec can be obtained even if the channel length is shortened.
As shown in Figure 5, the SS shows a relatively large value of SS > 70 mV/dec when the channel length is 20 nm. To obtain the condition of SS < 60 mV/dec, after reducing R = 3 nm and tox = 1 nm, the contour plot for Pr and Ec is shown in Figure 8. As can be seen in Figure 8, it can be observed that the SS < 60 mV/dec appears in the range of $15 \leqslant {P_r} \leqslant 23\,\mu C/c{m^2}$ and $0.95 \leqslant {E_c} \leqslant 1.5\,MV/cm$. As such, it can be observed that if the channel radius R and the oxide thickness tox are reduced, device parameters satisfying the value of SS < 60 mV/dec can be obtained even when the channel length is about 20 nm. However, the models for the quantum and tunneling effect are required when the channel length is less than 10 nm or the channel diameter is reduced to 7 nm [39,40,41,42,43], but further research on this should be conducted.
Observing Figures 7 and 8, it can be seen that the contours have a relationship of Pr=aEc (a is a proportionality constant) to maintain a constant SS value. That is, it can be seen that the SS according to a certain Pr/Ec value is constant. To observe this, Figure 9 shows the change of SS for the change of Pr/Ec value with the channel length as a parameter. As can be seen in Figure 9, it can be seen that the SS is plotted as a single value when Pr/Ec is determined in a given channel length. As mentioned in this section, the SS increases as the value of |Cfe| increases if Pr/Ec increases. It can be seen that the change of SS is relatively large according to Pr/Ec when the channel length is relatively short, 20 nm. As the channel length increased, the changing rate of SS for Pr/Ec decreased, and as Pr/Ec increased, the changing rate of SS for the channel length increased. Note that the SS is almost identical at Pr/Ec=10 pF/cm for channel lengths of 30 nm and 40 nm.
In this paper, an analytical SS model was presented to analyze the SS for junctionless GAA FET with ferroelectric. It has been found that the analytical SS model is valid since the SS value derived from the relation between drain current and gate voltage using a 2D potential distribution agrees well with the analytical SS model proposed here. In the case of the potential distribution represented by the Fourier-Bessel series in this paper, the case of n = 1 is dominant, so compared to the case of using n = 32, n = 1 could be used with a deviation of less than 1% according to the given conditions. As a result of SS analysis of junctionless GAA FET with ferroelectric using this analytical SS model, when the ferroelectric thickness increases at the same outer gate voltage, the voltage applied to the inner gate decreases as the voltage applied to the ferroelectric increases, and the flowing drain current decreases and SS also decreases. As the channel length increased, the change of SS according to the change of ferroelectric thickness relatively decreased. The decrease in channel radius results in a relatively greater ferroelectric thickness, resulting in a decrease in SS. As such, it can be seen that the SS value changes according to the relationship between the channel dimension and the ferroelectric thickness, and a result of SS < 60 mV/dec could be derived according to the device parameters when the ratio Pr/Ec between the remanent polarization Pr and the coercive field Ec decreases even in case of the channel length of 20 nm. In addition, it was found that the SS value was also constant at the given Pr/Ec. From the above results, it is judged that the analytical SS model presented in this paper can be used to analyze the SS of junctionless GAA FET with ferroelectric, and if the device parameters used in this paper are smaller, research on the quantum mechanical model should be conducted.
|
$ ∂Cn∂Vgs2=∂Cn∂Vgs1∂Vgs1∂Q∂Q∂Vgs2∂Dn∂Vgs2=∂Dn∂Vgs1∂Vgs1∂Q∂Q∂Vgs2∂Cn∂Vgs1=−2J1(αn)αn[J21(αn)+J20(αn)][exp(−αnL/R)−1]2sinh(−αnL/R)∂Dn∂Vgs1=−2J1(αn)αn[J21(αn)+J20(αn)][1−exp(αnL/R)]2sinh(−αnL/R)∂Vgs1∂Q=(∂Q∂Vgs1)−1=[−Cox2Lg[∞∑n=1[∂Cn∂Vgs1exp(αnLgR)−∂Dn∂Vgs1exp(−αnLgR)−∂Cn∂Vgs1+∂Dn∂Vgs1](Rαn)J0(αn)]]−1∂Q∂Vgs2=12αtfe+12βtfeQ2+30γtfeQ4+∂Vgs1∂Q∂∂Vgs2[exp(αnzmin/R)]=αnRexp(αnzmin/R)∂zmin∂Vgs2∂∂Vgs2[exp(−αnzmin/R)]=−αnRexp(−αnzmin/R)∂zmin∂Vgs2 $
|
Here, the zmin and derivative of zmin for Vgs2 can be obtained as the following.
| $ z_{\min } = \left(\frac{R}{2 \alpha_{1}}\right) \ln \left(\frac{D_{1}}{C_{1}}\right) $ |
|
$ ∂zmin∂Vgs2=(R2α1)∂∂Vgs2(lnD1−lnC1)=(R2α1)(∂lnD1∂Vgs1∂Vgs1∂Q∂Q∂Vgs2−∂lnC1∂Vgs1∂Vgs1∂Q∂Q∂Vgs2)=(R2α1)(∂lnD1∂Vgs1−−∂lnC1∂Vgs1)(∂Vgs1∂Q∂Q∂Vgs2)(R2α1)(∂lnD1∂Vgs1−∂lnC1∂Vgs1)=(R2α1)(2J1(α1)α1[J21(α1)+J20(α1)])[−[1−exp(α1L/R)]2D1sinh(−α1L/R)−−[exp(−α1L/R)−1]2C1sinh(−α1L/R)]=(R4α1sinh(−α1L/R))(2J1(α1)α1[J21(α1)+J20(α1)])[[exp(α1L/R)−1]D1+[exp(−α1L/R)−1]C1] $
|
The authors have not used Artificial Intelligence (AI) tools in the creation of this article.
The author declares that there is no conflicts of interest in this paper.
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Figures(1)
Bashir Sajo Mienda, Mohd Shahir Shamsir. Model-driven in Silico glpC Gene Knockout Predicts Increased Succinate Production from Glycerol in Escherichia Coli[J]. AIMS Bioengineering, 2015, 2(2): 40-48. doi: 10.3934/bioeng.2015.2.40
| Device parameter | Symbol | Value |
| Channel length | Lg | 20~60 nm |
| Channel radius | R | 5~10 nm |
| SiO2 thickness | tox | 1~2 nm |
| Doping concentration | Nd | 1018/cm3 |
| Ferroelectric thickness | tfe | 0~10 nm |
| Remanent polarization | Pr | 15~30 $ {\mathtt{μ}} $C/cm2 |
| Coercive field | Ec | 0.8~1.5 MV/cm |
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