Citation: Marek K. Korzeniowski, Barbara Baird, David Holowka. STIM1 activation is regulated by a 14 amino acid sequence adjacent to the CRAC activation domain[J]. AIMS Biophysics, 2016, 3(1): 99-118. doi: 10.3934/biophy.2016.1.99
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Increasing efficiencies of different cell technologies and decreasing cost of installations attracted photovoltaic (PV) systems for many applications [1]. For example, they became a mainstream power generation source bringing the total world capacity to 178 GW by 2014 [2]. Another area where PV applications are increasing is the electric car industry. In 2014, Ford has announced there concept car which has rooftop PV panels with special concentrators to charge the battery. The company said that the PV panels could provide power equal to a four-hour battery charge. Eindhoven University of Technology in Holland also announced their lightweight, wedge-shaped electric car that charges itself with PV cells. Rooftop PV panels on a car reduce the transfer of heat into the cabin by solar radiation in hot climates; thus reducing the heating of air temperature inside the car. This reduces the workload of the air conditioner, resulting in reduced fuel consumption (in a hybrid). Even though these cars provide a number of benefits, the efficiency of roof top PV panels will reduce with shading: as the shading is a dynamic process, an effective way of overcoming effects of shading is quite important.
Commonly used motors for hybrid and fully-electric vehicles are dc brushless and induction motors. They use motors having similar stators and are connected to the dc bus of the car through an inverter, usually operating on Pulse Width Modulation (PWM). This inverter requires a high voltage capacitor at the dc link and bulky filtering arrangements to eliminate unwanted harmonics. In order to overcome the limitations of PWM inverters and to facilitate PV connection, Imtiaz et. al (2013) proposed a celllevel power conversion topology based on a cascaded multi-level inverter [3]. In this inverter, a number of PV cells are connected together through H-bridge inverters. The outputs of each of different level H-bridge inverters are connected in series such that the synthesised waveform is almost a sinusoidal. Therefore the output has less harmonic distortion and switching losses are less compared to other inverter topologies [4].
A number of papers discuss different topologies, performance and control strategies for cascaded multi-level inverters [5,6,7,8]. Khajehoddin et. al in [9] presents a control strategy to control cascaded multi-level converters in a multi-string configuration for single-phase grid connected systems. The performance of symmetrical and asymmetrical single-phase cascaded multi-level inverters with respect to harmonics content, number of switches and voltage stress across the switch with photovoltaic cell as its input source is simulated in [10]. A 9-level cascaded multi-level inverter with solar energy using PWM technique that provides a high switching frequency is presented in [11]. Even though these papers discuss the performance and control of cascaded multi-level inverters, no paper discusses their shading performance.
In this paper, a cascaded multi-level inverter based PV system is presented and its shading performance is evaluated. In a PWM inverter based system, as a large number of cells are connected in series, shading a single cell causes the current in the string of cells to fall to the level of the shaded cell; thus reducing the generated PV power output [12]. In this proposed system, as each PV module (having lesser number of cells in series) generates a single voltage level in a step-wise output waveform, shading effects under partial shading conditions are expected to be much benign. Furthermore, as each string of cells is individually connected to an isolated H-bridge module, under fully shaded conditions the H-bridge can be controlled to by-pass the shaded module. The proposed system is simulated and a hardware prototype is implemented to validate the proposed system. Results are presented comparing the shading performance of the proposed system and a conventional PWM inverter system.
Figure 1 shows the 13-level cascaded multi-level inverter based PV system used for this study. Each phase of the three-phase 13-level inverter consists of six H-bridge units connected in series.
The principle of operation of the 13-level inverter is to synthesize the output voltage of each module to form a step-like ac voltage waveform across the output terminal. The ac voltage is produced by adding the output voltage of each module with different duty cycles. In general, with higher number of H-bridge modules in a single-phase structure, there will be more levels in the ac output voltage; thus producing an ac waveform closer to a sinusoidal wave. The number (M) of ac output voltage levels is given by M = 2N + 1, where N is the number of PV cells/modules. Then the output voltage, VO, of a single phase is given by,
VO=VO1+VO2+.....+VO(N−1)+VON | (1) |
In an H-bridge there are two modes of operations depending on the pattern of the switching signals. This is explained using semiconductor switching devices S 11, S 12, S 13, and S 14 of the top most Hbridge in Figure 1.
In the first mode, S 12 and S 14 are turned on to produce an output of +Vdc/6 and S 11 and S 13 are turned on to generate an output of -Vdc/6. The second mode gives an additional voltage level of 0 V: this occurs when the switch pairs S 12 and S 13, or S 11 and S 14, are turned on. The fundamental operation principle of the cascaded H-bridge multilevel inverter relies on the second mode of operation. In this mode, four switches in the H-bridge module is switched in four different sequences to generate a 3-level output voltage across output terminal of each H-bridge module as shown in Figure 2.
The output of the 13-level inverter is shown in Figure 3. This allows VO to vary between +Vdc and -Vdc in thirteen steps. This stair-case shape is obtained by switching individual bridges at different times corresponding to angles β1, β2, ...., and β6. Switching patterns are given in Table 1 and Table 2 for the positive half cycle and the negative half cycle respectively.
Inverter output voltage (V) | S 11 to S 61 | S 12 | S 22 | S 32 | S 42 | S 52 | S 62 | S 13 to S 63 | S 14 to S 64 |
Vdc/6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
2Vdc/6 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
3Vdc/6 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
4Vdc/6 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
5Vdc/6 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
6Vdc/6 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
Inverter output voltage (V) | S 11 | S 21 | S 31 | S 41 | S 51 | S 61 | S 12 to S 63 | S 13 to S 63 | S 14 to S 64 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-Vdc/6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-2Vdc/6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-3Vdc/6 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
-4Vdc/6 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
-5Vdc/6 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
-6Vdc/6 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
The switching delay angles, β1, β2, ...., β6 shown in Figure 3 are obtained by minimising the sum of the squared error between the actual output of the converter and a reference sinusoidal wave. Due to the symmetry of the output waveform, only one quarter cycle was considered in the optimization. The objective function of this optimisation algorithm is to minimise the following function:
∑T/4t=o△t(Vmaxsin(2πft)−Vdc6∑6i=6a1(t))2 | (2) |
Using this optimisation, it was found that β1 = 5°, β2 = 15°, β3 = 25°, β4 = 36°, β5 = 49° and β6 = 67°.
In the 13-level converter considered, the bridge switched on at the delay angle β1 will supply power from β1 to (π - β1). The PV module connected to this bridge will contribute more than any other PV module to form the stepwise ac waveform. On the other hand, the bridge switched at β6 will supply power from β1 to (π - β1) causing its PV module to contribute less than any other PV module when forming the stepwise ac waveform. In this operation, if a particular PV module is shaded, then it will always affect only a single step in the stepwise ac waveform. In order to circumvent the effect of shading on the output waveform, each bridge is switched on at different delay angle in each cycle. For example, the first bridge is switched on at β1 in the first cycle, at β2 in the second cycle, and at β6 in the sixth cycle. This equalises the contribution of all the PV modules over a period of six cycles on voltage waveform and the amount of energy supplied. The switching pulse generator achieves this by comparing the modulating signal with a stair-case carrier signal of period 6T with a six distinct voltage levels at sin(β1), sin(β2), sin(β3), sin(β4), sin(β5) and sin(β6) as shown in Figure 4. The width of each step of the carrier signal is equal to T. Figure 4 also illustrates how a switching signal is generated for S 13 (in Bridge 1). The 6-step stair-case carrier signal is compared to a sinusoidal modulating signal: when the modulating signal is greater than the carrier signal, the signal generator gives an output of 1; otherwise it gives an output of 0. To generate the switching signal to S 23 (in Bridge 2), the carrier signal in Figure 4 is shifted to the right by time T seconds, such that when the carrier signal of Bridge 1 is sin(β1), the carrier signal of Bridge 2 is sin(β2).
The structure of a single H-bridge module in the 13-level inverter is shown in Figure 5. It mainly consists of a separate PV module and four semiconductor switching devices. As the data were not available for the PV modules, its I-V characteristic was experimentally obtained and shown in Figure 6. The switching devices used were IRF840 MOSFETs. Other than a dc source and semiconductor switching devices, MOSFET driver ICs, Opto-couplers and dc-dc converters were used in this H-bridge module for signal isolation purposes.
An IR2110 MOSFET driver IC was used to produce necessary high-side and low-side gate signals for the H-bridge inverter. When cascading two H-Bridges, the gate signals provided to the second tier H-Bridge need to be boosted up further with respect to the ground. Since it is not practical to boost up gate signals of each H-Bridge, isolated gate signals were provided with respect to a reference point. To isolate the driver ICs, two dc-dc converters were used to provide isolated supply voltages (5 V and 15 V). Opto-couplers were used to isolate the signal level gate signals. The single H-bridge module was fabricated on a PCB as shown in Figure 7.
The implemented H-bridge module was tested under different loading conditions where the dc link voltage was supplied from a PV module. Figure 8 shows the output voltage waveform of a single H-bridge inverter in an open circuit condition and in a loading condition (a 6 Ω resistor was connected to the output as a load) respectively.
The 13-level inverter was implemented as a laboratory prototype by cascading six H-bridge modules. It comprises of six H-bridge modules having twenty four MOSFET (IRF840) switches along with their driver circuits. An STM32F4 discovery board was used as the control environment to generate gate pulses for the inverter switches.
The implemented 13-level inverter is shown in Figure 9. The inverter was tested under laboratory conditions and the setup is shown in Figure 10.
Figure 11 shows the experimental output waveform and frequency spectrum of the output of the multi-level inverter under the open circuit condition. Figure 12 shows the experimental output waveform and frequency spectrum under loaded conditions. The load was maintained nearly at the maximum power point. Note that, in order to show the harmonic components properly, the spectrum is zoomed in: thus the fundamental component, which is 1 pu, is not properly displayed.
The peak of the voltage of inverter was 25.2 V at the open circuit condition, where the dc link (PV module) voltages of each H-bridge module were kept at 4.3 V.
Figure 13 and Figure 14 show the amplitude spectrum and output voltage waveform of the inverter at loading condition when one PV module is shaded and when two PV modules are shaded respectively. It was found that when two PV modules are shaded, the third harmonic component was high and the fifth harmonic component was low.
The harmonic components that appear in the output voltage for different conditions are given in Table 3. When the amplitude spectrum of non-shaded condition is considered, it can be seen that the third harmonic component is low at loading condition than the open circuit condition. The amplitude spectrum of partially-shaded condition and fully-shaded condition of a single PV module has no reasonable variation.
Condition | Frequency | |||||
Normalized amplitude | ||||||
Fundamental | 2nd | 3rd | 5th | 7th | ||
No load | No shade | 1 | 0.008 | 0.053 | 0.018 | 0.008 |
1 module is shaded | 1 | 0.008 | 0.043 | 0.024 | 0.018 | |
2 modules are shaded | 1 | 0.01 | 0.038 | 0.008 | 0.038 | |
Loaded (I = 40 mA) | No shade | 1 | 0.005 | 0.028 | 0.023 | 0.018 |
1 module is shaded | 1 | 0 | 0.048 | 0.073 | 0.008 | |
2 modules are shaded | 1 | 0.018 | 0.106 | 0.018 | 0.013 | |
1 module is partially shaded | 1 | 0.058 | 0.05 | 0.077 | 0.008 |
The significance of the proposed cascaded multi-level topology, in contrast to a PWM inverter (a single-phase single H-bridge unit with uni-polar PWM switching) was appreciated by examining the effect of shading on the fundamental of the output voltage value for both topologies. Using FFT analysis on the output voltages, the output voltage’s fundamental component was evaluated; the results are shown in Figure 15. Here, shaded cells are randomly chosen. It can be observed that the fundamental voltage is significantly reduced in the conventional method as the shading is increased from 0% to 100%. However, the difference in the fundamental voltage levels between the two methods for same shading conditions is slightly reduced as the number of shaded cells are increased.
Consider the proposed modular approach with n number of levels. Therefore, the voltage across each bridge is Vdc/n; and the voltage across each semiconductor switch in blocking state (VT) is also Vdc/n. If the period of the fundamental is T1, according to Tables 1 and 2, the number of switches switched for a period of T1/2 is 2n.
Number of switches switched for a period of T1=2∗2n | (3) |
Assume that the switching loss associated with a switch is a linear function of on-state current (kiIT) and blocking state voltage (kvVT) across the switch such that the energy loss (Esw) can be approximated as follows (see Figure 16);
Esw=kvVT×kiIT×ktailIT | (4) |
Now, the total switching loss in the cascaded multi-level topology during a fundamental cycle is calculated as;
Ploss−SW,M=Esw∗4nT1 | (5) |
Noting that VT = Vdc/n in eq. (4), using eqs. (4) and (5), we have;
Ploss−SW,M=4k0VdcI2TT1 | (6) |
Now consider the PWM inverter; eq. (4) directly applies here as well. However, the total switching
loss is defined as follows for this case;
Ploss−SW,C=Esw∗4Tsw | (7) |
Now using eqs. (4) and (7) and identifying that VT = Vdc;
Ploss−SW,C=4k0VdcI2TTsw | (8) |
Finally, getting the ratio of the switching losses between the two methods, we have (the subscripts M and C refers to multi-level and PWM approaches);
Ploss−SW,CPloss−SW,M=T1Tsw=fswf1=fm | (9) |
With this result it is evident that the switching losses between the two approaches are ultimately defined by the frequency modulation ratio of the PWM approach. Therefore, in a qualitative sense, the number of levels in the modular approach has no effect on the ratio between the switching losses; however, it does have an effect on the absolute losses. As f1 is 50 Hz and fsw is usually selected around 1 - 2 kHz; fm is around 10-20. That is, the PWM inverter has 10-20 times more losses than that of the multi-level inverter.
The steady state current through the switches in on-state for both approaches is the same and equal to IT. Therefore, at a glance it seems that the multi-level approach causes higher conduction losses due to the increased number of semiconductor switches. However, note that the blocking voltage (VT) required in the multi-level approach is 1/n th of that of the conventional approach: i.e. Vdc/n. This means that for the multi-level approach, semiconductor switches with lower blocking voltages can be chosen; which have the advantageous characteristic of having lower on-state resistances (for power MOSFETs) or on-state voltages (for IGBTs):
Ploss−CON=I2T×Ronfor MOSFETSPloss−CON=VCE−on×ITfor IGBTs |
Therefore, the conduction losses associated with the switches would be actually lower than expected with the multi-level approach, provided that suitable semiconductor switches are chosen.
With the conventional approach, with the aid of the intermediate dc-link and appropriate control, the complete PV unit is operated at the maximum power. However, the proposed method, with individual switching of each cell based upon angle β, the maximum power is not always extracted from each cell. Instantaneous utilization of this power depends upon the current operating position within the fundamental cycle (i.e. how many units are turned on) and depends upon the used load conditions as well: see Figure 17. For example, when β = 30° (three units ON) and RL = 40 Ω, the operation point is at point x marked on the plot. Therefore, as far as the zero shading condition is concerned, the conventional method implies better power utilization.
On the other hand, in practical applications there will always be the effect of shading. In such cases, the contrast between the power utilization between the two approaches is quite different. In the modular approach, few redundant PV units are kept in the system to be used under shading conditions while the shaded unit is bypassed: therefore, the power utilization is unaltered in the modular approach.
However, the shading will affect the conventional approach due to the series connection of the PV units in the array. The effect of this on the two systems is illustrated in Figure 18. It is evident that the instantaneous power output of the conventional method deteriorates with the increasing number of shaded units in a series-connected array (due to the drop in the available total output voltage). Therefore, under shading conditions, the modular approach presents an appealing utilization of power: for instance, when 2 units are fully shaded, the modular approach offers an impressive advantage over the conventional method (see Figure 18).
PV systems are now considered as a promising option for electric vehicles. As these vehicles are constantly subjected to shading, and since the shading on cells is dynamically changing, a shadingproof inverter is ideally suited for such applications.
A development of a cascaded multi-level inverter based PV system is proposed for electric vehicle applications as a shading-proof inverter. The basic architecture and switching of the converter switches are described. A laboratory prototype of the proposed architecture was implemented using MOSFETs and harmonic performance under different shading conditions was evaluated. With a 13-level output, it was found that, except the third harmonic component, all the other voltage harmonics are below the values specified in the standards. It was also found that the third harmonic component increases with the shading on the cells/modules.
The shading performance, losses and power utilization of the cascaded multi-level inverter were compared with that of a conventional PWM inverter. From the results, it was found that the proposed inverter shows better immunity for shading than a PWM inverter. As the ratio of the losses of a PWM inverter to the proposed inverter is equal to the frequency modulation index, the switching losses of the proposed inverter is 1/10 th to 1/20 th of that of a PWM inverter. Furthermore, the conduction losses, when compared to a PWM inverter, can be optimized by properly selecting the blocking voltage of the semiconductor switches used. Even though the power utilization is compromised at full insolation, the power utilization performance of the proposed inverter is superior under shading conditions, thus ideally suited for electric vehicle applications.
The modular nature of the proposed inverter facilitates the cascading of more H-bridges with less cells/modules. This not only increases the number of steps in the synthesized sine wave, but also reduces the blocking voltage of the semiconductor switches. More levels will have a greater influence on the harmonic, shading, loss and power utilization performance of the proposed inverter.
The authors would like to thank the University of Peradeniya for the financial support through the grant RG/AF 2013/26/E.
All authors declare no conflicts of interest in this paper.
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1. | Yash Shukla, Zaid Ahmad Khan, Khan Mohammad, M Saad Bin Arif, 2024, Comparative Analysis of Selected Reduced Switch Count NPC Multilevel Inverter Topologies for Solar PV Applications, 979-8-3315-4158-3, 589, 10.1109/I3CEET61722.2024.10993910 |
Inverter output voltage (V) | S 11 to S 61 | S 12 | S 22 | S 32 | S 42 | S 52 | S 62 | S 13 to S 63 | S 14 to S 64 |
Vdc/6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
2Vdc/6 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
3Vdc/6 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
4Vdc/6 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
5Vdc/6 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
6Vdc/6 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
Inverter output voltage (V) | S 11 | S 21 | S 31 | S 41 | S 51 | S 61 | S 12 to S 63 | S 13 to S 63 | S 14 to S 64 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-Vdc/6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-2Vdc/6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-3Vdc/6 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
-4Vdc/6 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
-5Vdc/6 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
-6Vdc/6 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
Condition | Frequency | |||||
Normalized amplitude | ||||||
Fundamental | 2nd | 3rd | 5th | 7th | ||
No load | No shade | 1 | 0.008 | 0.053 | 0.018 | 0.008 |
1 module is shaded | 1 | 0.008 | 0.043 | 0.024 | 0.018 | |
2 modules are shaded | 1 | 0.01 | 0.038 | 0.008 | 0.038 | |
Loaded (I = 40 mA) | No shade | 1 | 0.005 | 0.028 | 0.023 | 0.018 |
1 module is shaded | 1 | 0 | 0.048 | 0.073 | 0.008 | |
2 modules are shaded | 1 | 0.018 | 0.106 | 0.018 | 0.013 | |
1 module is partially shaded | 1 | 0.058 | 0.05 | 0.077 | 0.008 |
Inverter output voltage (V) | S 11 to S 61 | S 12 | S 22 | S 32 | S 42 | S 52 | S 62 | S 13 to S 63 | S 14 to S 64 |
Vdc/6 | 0 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 |
2Vdc/6 | 0 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 |
3Vdc/6 | 0 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 |
4Vdc/6 | 0 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 |
5Vdc/6 | 0 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
6Vdc/6 | 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 |
Inverter output voltage (V) | S 11 | S 21 | S 31 | S 41 | S 51 | S 61 | S 12 to S 63 | S 13 to S 63 | S 14 to S 64 |
0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-Vdc/6 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-2Vdc/6 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 1 | 0 |
-3Vdc/6 | 1 | 1 | 1 | 0 | 0 | 0 | 0 | 1 | 0 |
-4Vdc/6 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 0 |
-5Vdc/6 | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 1 | 0 |
-6Vdc/6 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 0 |
Condition | Frequency | |||||
Normalized amplitude | ||||||
Fundamental | 2nd | 3rd | 5th | 7th | ||
No load | No shade | 1 | 0.008 | 0.053 | 0.018 | 0.008 |
1 module is shaded | 1 | 0.008 | 0.043 | 0.024 | 0.018 | |
2 modules are shaded | 1 | 0.01 | 0.038 | 0.008 | 0.038 | |
Loaded (I = 40 mA) | No shade | 1 | 0.005 | 0.028 | 0.023 | 0.018 |
1 module is shaded | 1 | 0 | 0.048 | 0.073 | 0.008 | |
2 modules are shaded | 1 | 0.018 | 0.106 | 0.018 | 0.013 | |
1 module is partially shaded | 1 | 0.058 | 0.05 | 0.077 | 0.008 |