Phase noise optimization of integrated ring voltage-controlled oscillators by metaheuristics

1.   Introduction

Complementary metal-oxide-semiconductor (CMOS) technology is very suitable for real applications, as for example in the design of CMOS image sensors ^[1]. This type of integrated circuit (IC) design involves analog and digital electronics, which static and dynamical characteristics can be accomplished by applying optimization techniques because a huge number of characteristics are in conflict. The CMOS design of analog ICs requires guaranteeing a proper static characteristic, which has been accomplished by applying optimization algorithms, as shown in ^[2]. This is not a trivial task in designing oscillators, as for the case of ring voltage-controlled oscillators (VCOs) that can be affected by process and temperature variations ^[3]. A VCO must work in a desired frequency range that is controlled by a voltage range, but it is dynamic so that one must find appropriate conditions to guarantee a robust design, e.g. guaranteeing minimum phase noise. Fortunately, metaheuristics are a good option to deal with problems whose target specifications are in conflict ^[4]. Another issue is considering constraints to reduce execution time of an optimization algorithm and improve convergence to the optimal solutions. In this manner, differential evolution (DE) and particle swarm optimization (PSO) algorithms have shown advantages in mono-objective optimization. For instance, the authors in ^[5] have shown that an objective condition may impose constraints on a design region, which make it difficult to find the exact optimal design, which can be solved by applying a multi-stage DE algorithm. In a similar direction, the authors in ^[6] introduced an improvement of PSO using artificial intelligence schemes. Both DE and PSO can also be combined as shown in ^[7].

VCOs find applications in a wide variety of integrated systems, so that they are very important blocks and henceforth its adequate design can greatly affect the performance of an application. From the IC design point of view, designing a ring VCO requires to take into account a variety of features that impact its electrical performance to different extents in accordance to a specific application that may require a wide frequency or voltage-control range. As mentioned above, process and temperature variations affect the dynamical behavior of a VCO, as well as other nonlinearities and second order effects that give place to identify trade-offs among IC design objectives ^[8,9]. Therefore, both the trade-offs to be considered and the desired target specifications to be accomplished are important issues to achieve an optimal performance of a desired application.

In this paper we highlight that a low phase noise performance is the main desired feature in the robust design of a ring VCO. In the state of the art one can find that phase noise reduction is a strong challenge for ring VCOs, and it has been approached through various techniques ^{[10,11,12,13,14]}. However, depending on the application, in some cases the most relevant features can be related to achieving high frequency operation, wide frequency and voltage-control tuning range, low power consumption, minimal silicon area, VCO gain linearity, or robustness to process, voltage and temperature (PVT) variations ^[15]. Enhanced performances for a desired application can be achieved by using certain circuit topologies. This paper is orienting the effort to minimize phase noise of a ring VCO ^[16]. On this direction, some previous works have achieved phase noise reduction by adding passive elements, such as inductors or resistors, to a basic VCO topology, as shown in ^[8,17,18]. However, this may come at the cost of tuning range reduction, increased power consumption or greater silicon area. Other techniques regarding phase noise reduction in VCOs are sub-sampling loops ^[11,19] that are applied in phase locked loops (PLLs). Superharmonic injection and current reuse ^[20,21], are also used for this purpose aiming also for power reduction, however these can also result in a reduced tuning frequency range. As one can infer, minimizing phase noise involves important dynamical characteristics in optimizing a ring VCO, so that this is not a trivial task.

Through using optimization algorithms an IC designer can asses both the specifications and objectives simultaneously. Nowadays, algorithms such as machine learning have been used for minimizing phase noise in a VCO considering PVT variations ^[22]. Other, previous and related works have employed metaheuristics to achieve phase noise minimization, some of them have combined optimization algorithms in conjunction with symbolic modeling, such as PSO, non-dominated sorting genetic algorithm (NSGAII), multi-objective particle swam optimization (MOPSO) and infeasibility-driven evolutionary algorithm (IDEA), to minimize both the phase noise and power consumption ^[23,24]. Given that mono-objective algorithms are suitable for continuous optimization problems, such as the sizing of CMOS ICs ^[25,26], and that the only objective for this case study is phase noise, mono-objective algorithms are selected to carry out the optimization. This is also due to the fact that since they use all of its capacity in the enhancement of a particular objective instead of purposing its power for the improvement of multiple objectives they can provide better results for the one objective ^[27]. Henceforth, two mono-objective algorithms, DE and PSO, are used herein with the objective to minimize phase noise in a ring VCO ^[28], which also accounts for trade offs, thus maintaining important features, such as minimum power consumption. It is important to mention that the use of metaheuristics for VCO optimization, such as DE and PSO, aims to offer the designer the possibility to redefine the algorithm's objective and constraints to the ones that are relevant to a particular application, without having to implement further design changes.

The paper organization is described next: Section 2 outlines the basis of DE and PSO algorithms. A brief description of the CMOS ring VCO to be optimized is presented in Section 3. The optimization algorithms adapted to minimize phase noise in a ring VCO are described in Section 4. Section 5 summarizes the optimization results. At last, the conclusions are presented in Section 6.

2.   DE and PSO algorithms

2.1.   Differential evolution

Differential evolution (DE) algorithm is based on the concept of individuals population's evolution through competition, by applying this conception an iterative optimization is carried out. The initial population is constituted by randomly generated individuals, each one of them represents a tentative solution. The individuals suitability for a particular problem is given by a fitness value, the relation between the individual and its fitness value is given by an objective function. New offsprings are generated by reproducing the individuals with better fitness (parents) by employing genetic operators, such as crossover and mutation which lead the algorithm towards finding suitable solutions. The survival of the offsprings is determined upon evaluation. The aforementioned process constitute a generation, and it keeps evolving until a stop criteria is met ^[4,29].

Individuals are represented through vectors of real numbers, which are maintained within the defined limits of each design variable. If a design variable's value is not within the limits scope, the recombination and mutation operators can be used to reset the value. The algorithm's performance can be tuned to a faster convergence through its constants calibration. Through the optimization process each individual is mutated to generate an adaptive solution $v_{ij}$ from three randomly chosen parents, as shown in (2.1). Subsequently, the crossover produces a trial solution through the recombination of a mutated solution $v_{ij}$ with an individual $x_{ij}$, as done in (2.2). Last but not least, the replacement takes place by an elitist selection, which means that if the new individual's fitness value is better or equal to the parent, then the later will be replaced, as shown in (2.3) ^[4].

2.2.   Particle swarm optimization

PSO is a mono-objective metaheuristic, that has been widely used for CMOS IC design. PSO initialization is performed from a particle disposition randomly generated within a defined search space, each particle is defined by its velocity and position ^[30]. The particles' velocity and position are represented by mathematical expressions. Regarding the particles' position, it varies through iterations from an initial velocity vector. Given that each particle recognizes its best position and determines if its actual position is the global best or if it is not, the particle's updating is based on both the particles' position and speed ^[25]. The particle's updating expressions are given by (2.4) and (2.5), where $p_{i}(t+1)$ and $v_{i}(t+1)$ are the particle's position and velocity at the $i_{th}$ iteration, respectively. $p_{best_i}$ and $g_{best}$ represent the particle's best position and best global position, respectively. $c_{1}$ and $c_{2}$ depict the reliability of the particle in itself and in the swarm, respectively. Lastly, $r_{1}$ and $r_{2}$ are both real randomly generated numbers with a uniform distribution ranging within $0$ and $1$.

The balance between exploration and exploration tendencies is given by constants $c_{1}$ and $c_{2}$. A rise in $c_{1}$ produces the particles to go towards its best local experiences, whereas an increase in $c_{2}$ results in faster convergence to the global best position ^[30]. Two factors that highly influence the achievement of global optimality are the selection of the best solutions that guarantees that an optimal value is reached, the other one is randomization, which prevents the solution from being stopped at optimum local values ^[31].

3.   CMOS ring VCO

The case study of this paper is the phase noise minimization of the CMOS ring VCO topology shown in Figure 1(a) ^[32], this CMOS VCO is designed herein with a pseudo differential architecture using an IC technology of 180 nanometers (nm) from United Microelectronics Corporation (UMC). The VCO is implemented using the inverters shown in Figure 1(c) as delay cells, it is also composed by inverter caps, shown in Figure 1(b). Inverter caps are used to tune the VCO's oscillation frequency by varying the variable capacitance of the inverter's gate. Inverter caps benefit from having a desirable jitter performance, this is because they keep a fixed capacitance value through PVT variations ^[32]. Figure 2(a) shows the capacitance offered by the inverter cap circuit through the $V_{gate}$ variation, the VCO tuning characteristics are shown in Figure 2(b).

Before optimization of the VCO, it features -93.1 dBc/Hz @1MHz phase noise to begin with, an oscillating frequency centered at 1.66 GHz with a 0.3 V control voltage, as shown in Figure 3.

The transistors' sizes of the CMOS ring VCO preliminary design using an IC technology of 180 nm from UMC are: The inverter transistors have a gate channel width of $W_{MN1} = 9.45\; \mu m$, $W_{MP1} = 23.4\; \mu m$, and a gate channel length of $L_{MN1} = L_{MP1} = 0.27\; \mu m$. The inverter cap transistors sizes were set to $W_{MN2} = W_{MP2} = L_{MN2} = L_{MP2} = 2.7\; \mu m$. Thus resulting in oscillation frequencies between 1.68 GHz and 1.56 GHz, for voltages-control ranges between $-0.2\; V$ and $-0.9 V\;$, respectively. The power consumption for this oscillator is around 11.34 mW at its highest frequency.

4.   Optimization process description

In ^[9], the authors discussed a bi-objective problem considering that for an LC-VCO there is a trade-off between phase noise and power consumption, and both are minimized. Recent works show that DE ^[33] and PSO ^[34], can be improved. In this paper, the phase noise of the CMOS ring VCO shown in Figure 1(a) is minimized by applying DE and PSO algorithms. In this optimization problem, defined by (4.2), the single objective function is formulated as the phase noise minimization. Whereas the design variables, $x$, are constituted by the dimensions of both the inverter ($W_{MP1}$, $W_{MN1}$, $L_{MN1}$, $L_{MP1}$) and the inverter cap (in which case $W_{M2} = W_{MN2} = W_{MP2} = L_{MN2} = L_{MP2}$), as well as the voltage control range. The constraints are given by the operation region of the inverter MOS transistors ^[2], by the minimum frequency and maximum power consumption. The sizing optimization problem finds the most suitable sizes of the design variables that are within the defined search ranges, considering the restrictions' compliance.

For DE algorithm the objective function $g(x)$ in (4.2) is given by (4.1), where $\mu$ is a tunable constant that in this case is set to one, $r(x)$ represents the constraints and lastly $f(x)$ equals phase noise. Moreover, in the DE objective function, a flag sets a value of $0$ or $1$ for fulfilled and non fulfilled constraints, respectively, this means that when all of the restrictions are met the objective function is only determined by phase noise $g(x) = f(x)$. For the PSO algorithm the objective function is solely defined by the phase noise, meaning that for PSO $g(x) = f(x)$.

In both DE and PSO algorithms optimization processes, the phase noise measurement is carried out afterwards of the VCO simulation, where the operation region of the MOS transistors ^[2], the power consumption, and the oscillation frequency, are obtained. This is important, since the magnitude of the latter is required to measure phase noise through the HSPICE$^{TM}$ RF command ".phasenoise". On the other hand, when the restrictions are not satisfied in the first run (e.g. VCO's oscillation frequency is lower than $f_{min}$, power consumption is greater than $P_{max}$ or if the inverter MOS transistors are not working in the appropriate operation region) a high value is assigned to the VCO automatically. In this work, both algorithms DE and PSO provide good results by establishing this high value as phase noise = $10^9$, and it is assigned in both cases: When the constraints are not met and/or when the phase noise simulation fails.

The sizing optimization process to minimize phase noise briefly described above, is adapted in the Algorithm 1 to use DE as the optimization method. For DE, the individuals from the randomly generated population are added to the VCO's netlist and each one of them is simulated. The SPICE simulator is linked within the optimization loop to evaluate the VCO electrical characteristics. From the output *.lis file, the electrical characteristics are extracted to monitor the constraint values, when these are indeed satisfied the solution is considered feasible and the VCO is simulated again with the same individuals. This new simulation features the addition of the necessary commands to execute phase noise simulation to the VCO netlist. Whereas if the constraints are not fulfilled, the solution is unfeasible and then the phase noise, $f(x)$, is set to a high value.

Algorithm 2 ^[25], shows the transformation of the PSO algorithm for the specific optimization problem of minimizing a ring VCO's phase noise, which means that $g(x) = L \{ f_{offset} \}$. Similarly to the process followed with the DE algorithm, with PSO the particles of the randomly generated population are replaced into the VCO's netlist. When the VCO design does not comply with the restrictions, a high value is assigned to the objective function, which is the phase noise. If the VCO does satisfy the constraints, then the phase noise is evaluated. The updating mathematical expressions are given by (2.4) and (2.5).

In PSO the constraint management considers that: when two feasible particles are compared, the particle with the lowest phase noise is selected, if only one of the particles is feasible, then the feasible one is chosen. Lastly, when both particles are not feasible then the particle that complies with more constraints is selected ^[25].

The limits of the search spaces of the design variables for both DE and PSO algorithms are: $2\; \lambda \leq W \leq 1000\; \lambda$ and $2\; \lambda \leq L \leq 10\; \lambda$ for widths and lengths, respectively, where $\lambda$ = 90 nm. The control voltage range is set to be from rail-to-rail, $V_{SS} \leq V_{ctrl} \leq V_{DD}$, where $V_{SS} = -0.9\; V$ is the lower supply voltage and $V_{DD} = 0.9\; V$ the higher supply voltage. The frequency and power constraints are set to $f_{min} = 100\; MHz$ and $P_{max} = 30\; mW$, respectively in both algorithms. The optimization with DE and PSO algorithms requires to define a population of $I_n$ individuals or particles, a maximum number of generations $maxGen$ and an objective function $g(x)$.

5.   Optimization results

DE algorithm executions are carried out setting the number of individuals $I_n$ and amount of generations $max_{gen}$ to $30$ and $30$ respectively. For the PSO algorithm a population of $60$ individuals and a maximum number of generations of $40$ are used. The design parameters of each of the 5 best feasible sized solutions for both algorithms as well as the simulated phase noise (PN), frequency and power of the VCO, are summarized in Table 1. For this purpose, the best solutions are considered to be the ones with the lower phase noise.

The phase noise simulation results of the non-optimized design (-93.1 dBc/Hz@1MHz) against the best solution given by the DE (-129.01 dBc/Hz@1MHz) and the PSO (-124.67 dBc/Hz@1MHz) algorithms are shown in Figure 4. The blue signal depicts the original phase noise, whereas the green and orange signals depict the DE and the PSO phase noise, respectively. From Table 1 and Figures 3 and 4 it is noticeable the improvement of 35.91 and 31.57 dBc/Hz@1MHz, with respect to the original design phase noise, for DE and PSO algorithms, respectively. It can be seen that DE algorithm achieved lower phase noise compared to PSO, while requiring less resources to achieve better results. Another point is that compared to DE, PSO required to increase both the population size and the maximum number of generations to 60 and 40, respectively. Additionally, PSO algorithm required approximately two to three times the execution time of DE to generate similar feasible solutions. Finally, to appreciate the usefulness of performing a minimization of phase noise, Table 2 shows a comparison of some relevant parameters in VCO performance of the best sizing result provided by the DE algorithm with other ring VCO topology results in the literature. As one can see, the phase noise performance of the design obtained through optimization with the DE algorithm is comparable to what is already reported in the literature for designs implemented in the same technology and measured at the same offset frequency, while also represents an improvement from the phase noise performance of the non-optimized design.

6.   Conclusions

The optimization of the phase noise performance of an eight stage pseudo-differential CMOS ring VCO through two mono-objective metaheuristics, DE and PSO, was carried out in this paper. Through the optimization process it became noticeable that compared to PSO, the optimization problem was solved more effectively with the DE algorithm, since it gave better results in terms of a lower phase noise while requiring less resources (the problem was solved with a smaller population size and a lower number of maximum generations) and execution time. Also, from the presented results one can see the improvement on phase noise provided by DE and PSO, compared to the preliminary (manual) design.

Acknowledgments

Perla Rubi Castañeda-Aviña acknowledges CONACYT for PhD scholarship under CVU 852177.

Conflict of interest

The authors declare no conflicts of interests.