Promotion of anti-disturbance capability in UPQC systems under FCS-MPC control with LADRC-optimized phase-locked loop

Yuting Yu; Muhammad Murtadha Othman; Yanting Chu; Ismail Musirin; Yuting Yu; Muhammad Murtadha Othman; Yanting Chu; Ismail Musirin

doi:10.3934/electreng.2026018

AIMS Electronics and Electrical Engineering

2026, Volume 10, Issue 3: 446-472. doi: 10.3934/electreng.2026018

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Promotion of anti-disturbance capability in UPQC systems under FCS-MPC control with LADRC-optimized phase-locked loop

1.
Universiti Teknologi MARA, Faculty of Electrical Engineering, 40450 Shah Alam, Selangor, Malaysia
2.
Hunna Railway Professional Technology College, Shifeng, Zhuzhou, Hunan 412001, China

Academic Editor: Fanny Spagnolo

Received: 27 November 2025 Revised: 13 March 2026 Accepted: 23 April 2026 Published: 09 June 2026

In three-phase three-wire power systems, unified power quality conditioners (UPQCs) compensate for current/voltage fluctuations while enhancing load-side power quality. However, current solutions face three key limitations: (1) limited responsiveness to rapid disturbances, (2) sensitivity to grid variations, and (3) inadequate phase-locked loop (PLL) performance, all of which undermine compensation effectiveness. Traditional proportional-integral (PI) controllers further exacerbate these issues through overshooting during control quantity disturbances. This paper proposes an enhanced finite control set model predictive control (FCS-MPC) system integrated with linear active disturbance rejection control (LADRC) to improve UPQC's anti-disturbance capabilities. The architecture combines a series active power filter (APF)-side voltage compensation module based on FCS-MPC, a shunt APF-side current compensation module based on FCS-MPC, and a LADRC-optimized mixed second/third-order generalized integrator-based PLL (MSTOGI-PLL). Through rigorous MATLAB/Simulink simulations, the proposed UPQC demonstrates superior robustness compared to conventional controllers, achieving 85% voltage sag compensation within 12.5 ms response time. Simulation result validation confirms that the LADRC-enhanced FCS-MPC system significantly improves disturbance rejection, yielding effectively reduced voltage total harmonic distortion (THD) and enhanced post-compensation power quality across various grid anomalies.
Citation: Yuting Yu, Muhammad Murtadha Othman, Yanting Chu, Ismail Musirin. Promotion of anti-disturbance capability in UPQC systems under FCS-MPC control with LADRC-optimized phase-locked loop[J]. AIMS Electronics and Electrical Engineering, 2026, 10(3): 446-472. doi: 10.3934/electreng.2026018

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Abstract

In three-phase three-wire power systems, unified power quality conditioners (UPQCs) compensate for current/voltage fluctuations while enhancing load-side power quality. However, current solutions face three key limitations: (1) limited responsiveness to rapid disturbances, (2) sensitivity to grid variations, and (3) inadequate phase-locked loop (PLL) performance, all of which undermine compensation effectiveness. Traditional proportional-integral (PI) controllers further exacerbate these issues through overshooting during control quantity disturbances. This paper proposes an enhanced finite control set model predictive control (FCS-MPC) system integrated with linear active disturbance rejection control (LADRC) to improve UPQC's anti-disturbance capabilities. The architecture combines a series active power filter (APF)-side voltage compensation module based on FCS-MPC, a shunt APF-side current compensation module based on FCS-MPC, and a LADRC-optimized mixed second/third-order generalized integrator-based PLL (MSTOGI-PLL). Through rigorous MATLAB/Simulink simulations, the proposed UPQC demonstrates superior robustness compared to conventional controllers, achieving 85% voltage sag compensation within 12.5 ms response time. Simulation result validation confirms that the LADRC-enhanced FCS-MPC system significantly improves disturbance rejection, yielding effectively reduced voltage total harmonic distortion (THD) and enhanced post-compensation power quality across various grid anomalies.

References

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