Research on post-equalization technology of a visible light communication system based on improved LSTM model and FPGA

Ke Xiong; Ke Xiong

doi:10.3934/math.2026169

AIMS Mathematics

2026, Volume 11, Issue 2: 4220-4242. doi: 10.3934/math.2026169

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Research on post-equalization technology of a visible light communication system based on improved LSTM model and FPGA

Ke Xiong ^{1,2
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1.
Application Management Department, Digital and Intelligent Operation Center, Guangdong Power Grid Co., Ltd., Guangzhou 510000, China
2.
School of Information Science and Technology, University of Science and Technology of China (USTC), Hefei 230026, China

Received: 27 October 2025 Revised: 16 January 2026 Accepted: 22 January 2026 Published: 10 February 2026
MSC : 68T07, 94A12

In this study, I proposed a post-equalization method for high-speed visible light communication (VLC) systems using an improved long short-term memory (LSTM) model jointly optimized with a field-programmable gate array (FPGA) to address nonlinear distortion, multipath interference, and model deployment complexity. The LSTM structure was simplified by merging three gates into two and compressing the hidden state to 64 dimensions, while 8-bit fixed-point quantization reduced computational cost. The received signal was divided into a 32-point sliding buffer and aligned in zero phase for precise temporal-symbol matching. The computational graph was modularized into matrix operations, activation, and state update stages, each implemented as dedicated FPGA modules in a three-stage pipeline on an Artix-7 platform. Through loop unrolling and resource sharing, the design achieved a 16-cycle inference latency at 100 MHz with minimal logic utilization. Experimental results demonstrated superior performance, with symbol error rate (SER) ≤ 0.0031 and normalized mean square error (NMSE) ≤ 0.0115 across LED drive currents. Under 8-PAM modulation, total harmonic distortion (THD) and error vector magnitude (EVM) were maintained at 3.45% and 4.32%, respectively, showing enhanced nonlinear tolerance and equalization stability. As the multipath delay spread increased from 5 ns to 25 ns, the average intersymbol interference ratio (ISI-Ratio) improved from 20.7 dB to 28.4 dB, and the dynamic timing error (DTE) remained within 1.82 × 10^-3–3.14 × 10^-3. The lookup table (LUT) usage was kept within 78.2% ± 0.9%, and the inference latency was (0.160 ms ± 0.003 ms). These results indicated that the proposed method effectively mitigates multipath effects and achieves an optimal trade-off between algorithmic compactness and hardware efficiency, providing a closed-loop optimization pathway for intelligent equalization in resource-constrained optical communication systems.
- post-equalization technique,
- communication system,
- long short-term memory,
- field-programmable gate array,
- visible light communication
Citation: Ke Xiong. Research on post-equalization technology of a visible light communication system based on improved LSTM model and FPGA[J]. AIMS Mathematics, 2026, 11(2): 4220-4242. doi: 10.3934/math.2026169

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Abstract

In this study, I proposed a post-equalization method for high-speed visible light communication (VLC) systems using an improved long short-term memory (LSTM) model jointly optimized with a field-programmable gate array (FPGA) to address nonlinear distortion, multipath interference, and model deployment complexity. The LSTM structure was simplified by merging three gates into two and compressing the hidden state to 64 dimensions, while 8-bit fixed-point quantization reduced computational cost. The received signal was divided into a 32-point sliding buffer and aligned in zero phase for precise temporal-symbol matching. The computational graph was modularized into matrix operations, activation, and state update stages, each implemented as dedicated FPGA modules in a three-stage pipeline on an Artix-7 platform. Through loop unrolling and resource sharing, the design achieved a 16-cycle inference latency at 100 MHz with minimal logic utilization. Experimental results demonstrated superior performance, with symbol error rate (SER) ≤ 0.0031 and normalized mean square error (NMSE) ≤ 0.0115 across LED drive currents. Under 8-PAM modulation, total harmonic distortion (THD) and error vector magnitude (EVM) were maintained at 3.45% and 4.32%, respectively, showing enhanced nonlinear tolerance and equalization stability. As the multipath delay spread increased from 5 ns to 25 ns, the average intersymbol interference ratio (ISI-Ratio) improved from 20.7 dB to 28.4 dB, and the dynamic timing error (DTE) remained within 1.82 × 10^-3–3.14 × 10^-3. The lookup table (LUT) usage was kept within 78.2% ± 0.9%, and the inference latency was (0.160 ms ± 0.003 ms). These results indicated that the proposed method effectively mitigates multipath effects and achieves an optimal trade-off between algorithmic compactness and hardware efficiency, providing a closed-loop optimization pathway for intelligent equalization in resource-constrained optical communication systems.

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