Export file:

Format

  • RIS(for EndNote,Reference Manager,ProCite)
  • BibTex
  • Text

Content

  • Citation Only
  • Citation and Abstract

Different retiming transformation technique to design optimized low power VLSI architecture

1 Department of Electronics and Communication, Research Scholar, Visvesvaraya Technological University, Bangalore Institute of Technology, Bangalore, India
2 Department of Electronics and Communication, Bangalore Institute of Technology, Bangalore, India

A different method for designing low power retime architecture is presented in this paper. The modified retiming transformation techniques approach to reduce the dynamic power consumption of the digital circuit, without compromising the output results. In this paper, retiming transformation is extended in two-ways to reduce the power consumption of the design. Graphical Circular Retiming and Tabular Shift Retiming are the two methods used to realize how the registers are mapped to reduce the glitching power. Proposed transformation technique delay value is placed in the form of metric and verified without sacrificing the functionality. Proposed transformation technique is applied to FIR filter to analyze the simulation and synthesis results as proofs of this concept. Experimental results are compared with the conventional retiming transformation technique with the same operating frequency, and with the significant reduction in dynamic power of FIR filter.
  Figure/Table
  Supplementary
  Article Metrics

Keywords graphical retiming transformation; tabular retiming transformation; reduction in dynamic power

Citation: Jalaja S, Vijaya Prakash A M. Different retiming transformation technique to design optimized low power VLSI architecture. AIMS Electronics and Electrical Engineering, 2018, 2(4): 117-130. doi: 10.3934/ElectrEng.2018.4.117

References

  • 1. Mittal A, Nandi A and Yadav D (2017) Comparative study of 16-order FIR filter design using different multiplication techniques. IET Circ Device Syst 11: 196–200.    
  • 2. Rashidi B (2013) High performance and low-power finite impulse response filter based on ring topology with modified retiming serial multiplier on FPGA. IET Signal Process 7: 743–753.    
  • 3. Mohanty BK and Meher PK (2016) A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications. IEEE Transactions on Very Large Scale Integration Systems 24: 444–452.    
  • 4. Leiserson CE, Rose FM and Saxe JB (1983) Optimizing synchronous circuitry by retiming. 3rd Caltech conference on VLSI, pp. 87–116, Springer, Berlin, Heidelberg.
  • 5. Leiserson CE and Saxe (1991) Retiming synchronous circuitry. Algorithmica 6: 5–35.    
  • 6. Chen JJ, Chip-Hong C, Feng F, et al. (2015) Novel Design Algorithm for Low Complexity Programmable FIR Filters Based on Extended Double Base Number System. IEEE T Circuits- I 62: 224–233.
  • 7. Monteiro JC, Devadas S and Ghosh A (1993) Retiming sequential circuits for low power. Proceedings of the IEEE/ACM International conference on Computer-Aided Design, 398–402.
  • 8. Parhi KK (2007) VLSI digital signal processing systems: design and implementation. John Wiley and Sons.
  • 9. Aksoy L, Flores PF and Monteiro JC (2014) Efficient Design of FIR Filters Using Hybrid Multiple Constant Multiplications on FPGA. 2014 IEEE 32nd International Conference on Computer Design (ICCD), 42–47.
  • 10. Meidani M and Mashoufi B (2016) Introducing new algorithms for realising an FIR filter with less hardware in order to eliminate power line interference from the ECG signal. IET Signal Process 10: 709–716.    
  • 11. Meher PK (2016) On Efficient Retiming of Fixed Point Circuits. IEEE Transactions on Very Large Scale Integration Systems 24: 1257–1265.    
  • 12. Park SY and Meher PK (2014) Efficient FPGA and ASIC Realizations of a DA-Based Reconfigurable FIR Digital Filter. IEEE T Circuits-II 61: 511–515.
  • 13. Lou X, Yu YJ and Meher PK (2016) Analysis and Optimization of Product-Accumulation Section for Efficient Implementation of FIR Filters. IEEE T Circuits-II 63: 1701–1713.
  • 14. Kang Y, Kim J and Kang S (2016) Novel Approximate Synthesis Flow for Energy-efficient FIR Filter. 2016 IEEE 34th International Conference on Computer Design (ICCD), 96–102.
  • 15. Pan Y and Meher PK (2014) Bit-Level Optimization of Adder-Trees for Multiple Constant Multiplications for Efficient FIR Filter Implementation. IEEE T Circuits-I 61: 455–462.    

 

Reader Comments

your name: *   your email: *  

© 2018 the Author(s), licensee AIMS Press. This is an open access article distributed under the terms of the Creative Commons Attribution Licese (http://creativecommons.org/licenses/by/4.0)

Download full text in PDF

Export Citation

Copyright © AIMS Press All Rights Reserved